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OMAP3530 and MSBSP Troubles.

Other Parts Discussed in Thread: OMAP3530, CCSTUDIO

Hello,

I will start with this is my first time attempting to work with the OMAP3530....

I am attempting what I thought would be a relatively simple task of configuring MCBSP1 on the OMAP3530.  I am utilizing CCSv4 with a Mistral EVM Rev G Board (and corresponding board support in CCS) as well as a Spectrum Digital XDS510 USB Emulator. 

What I am simply trying to do is get a free running tx clock which I can sample on a scope but thus far I am having 0 luck.  I have managed to get the DSP out of reset and load the application on, step through etc but I get nothing on the output clock pins.  More over when I inspect the memory locations as I step over them in the debugger they do not seem to be changing at all (i.e. I cannot seem to modify the MCBSP control registers at all).

The following is the "simple" code that I am running.  I have done very similar things on the OMAPL137 without issue..

Any help would be greatly appreciated.

#define MCBSP1_BASE  0x48074000

#define MCBSP_PCR_REG        0x48074048
#define MCBSP_SPCR1_REG     0x48074014
#define MCBSP_SPCR2_REG     0x48074010
#define MCBSP_RCR1_REG       0x4807401C
#define MCBSP_XCR1_REG        0x48074024
#define MCBSP_SRGR1_REG        0x4807402C
#define MCBSP_MCR1_REG        0x48074034
#define MCBSP_RCERA_REG        0x48074038
#define MCBSP_XCERA_REG        0x48074040

void main(int argc, const char * argv[])
{

    MCBSP_SPCR1_REG     = 0x00410021;
    MCBSP_RCR1_REG     = 0x00002220;
    MCBSP_XCR1_REG     = 0x00000000;
    MCBSP_SRGR1_REG     = 0x20000008;
    MCBSP_MCR1_REG        = 0x00000000;
    MCBSP_RCERA_REG     = 0x00000000;
    MCBSP_XCERA_REG     = 0x00000000;
    MCBSP_PCR_REG         = 0x00000201;   

    for(;;);

}

 

  • Matthew

    Welcome to the world of OMAP!

    The first thing I notice from your code is that you are programming reserved bits in the SPCR1_REG (0x00410021) and SRGR1_REG (0x20000008). The bits should not be set.

    Next, your code does not start the frame sync generator. You need to set SPCR2.GRST to enable the clock. You’d also need to set SPCR2.FRST if you want to generate frame signals. You should now have a free running clock on McBSP1_CLKX.

    Things to consider are:
    Clock source   (SRGR2.CLKSM & PCR.SCLKME & CONTROL_DEFCONF0.MCBSP1_CLKS)
    Clock divider  (SRGR1.CLKGDV)
    Clock polarity (PCR.CLKXP)

    What values do you read from the registers before and after you have written to them? Default values?
    One possibility is that you have not enabled the module clocks.
        PRCM.CM_FCLKEN1_CORE[9] EN_MCBSP1

        PRCM.CM_ICLKEN1_CORE[9] EN_MCBSP1

    BRs
      Paul

     

  • Hey Paul,

     

    Thanks for the input.  It has been a very bumpy road thus far :)

    I have done some rework of what I had started with after spending many hours reading the 3400 page OMAP3530 manual... great fun.  I have made it a bit further by setting the clocks up correctly (or what appears to be correctly) so now I can actually see the registers in the memory pane of CCS (not the registers pane for some reason though.  for this device it only seems to show core and paired registers... but I guess that is a different problem).  All registers seem to be correct but I am after everthing is said and done I still do not seem to get a tx clock (I am measuring on the external bus on the Mistral OMAP3 EVM board).  Would you mind taking a peek at this and see if there are any glaring problems that might be restricting me.

     

    Thanks again for your help,

    Matt


    #define MASK_BIT(bit) \
            (1 << (bit))


    typedef volatile unsigned int * const devPtr;

    #define MCBSP1                 0x48074000
    #define FLCKEN1_CORE        0x48004A00
    #define ILCLKEN1_CORE        0x48004A10
    #define CM_CLKSEL1_PLL        0x48004D40

    #define _96M_SRC 0x40

    #define MCBSP_PCR_REG        0x00000048
    #define MCBSP_SPCR1_REG     0x00000014
    #define MCBSP_SPCR2_REG     0x00000010
    #define MCBSP_RCR1_REG       0x0000001C
    #define MCBSP_XCR1_REG        0x00000024
    #define MCBSP_SRGR1_REG        0x0000002C
    #define MCBSP_SRGR2_REG        0x00000028
    #define MCBSP_MCR1_REG        0x00000034
    #define MCBSP_RCERA_REG        0x00000038
    #define MCBSP_XCERA_REG        0x00000040
    #define MCBSP_XCCR_REG        0x000000AC

    #define REGISTER_ACCESS(root, offset) *(devPtr)(root + offset)

    void main(int argc, const char * argv[])
    {
        int value = 0;
        int i = 0;
           
        REGISTER_ACCESS(CM_CLKSEL1_PLL, 0) |= _96M_SRC;   
        REGISTER_ACCESS(FLCKEN1_CORE, 0) |= MASK_BIT(9);  //Enable MCBSP1
        REGISTER_ACCESS(ILCLKEN1_CORE, 0) |= MASK_BIT(9); //Enable MCBSP1
       
        REGISTER_ACCESS(MCBSP1, MCBSP_SPCR1_REG) &= ~MASK_BIT(0); //Reset
        REGISTER_ACCESS(MCBSP1, MCBSP_SPCR2_REG) &= ~MASK_BIT(0); //Reset
       
        //Reset the sample rate generator
        REGISTER_ACCESS(MCBSP1, MCBSP_SPCR2_REG) &= ~MASK_BIT(6);
       
        //Master Transmitter - set Frame Sync XM on
        REGISTER_ACCESS(MCBSP1, MCBSP_PCR_REG) |= MASK_BIT(11);        //FSXM    (1)
        //Frame-Synchronization pulses generated by an external device.
        REGISTER_ACCESS(MCBSP1, MCBSP_PCR_REG) &= ~MASK_BIT(10);    //FSRM  (0)       
        //Transmit Clock is an output pin and is driven by the internal SRG
        REGISTER_ACCESS(MCBSP1, MCBSP_PCR_REG) |= MASK_BIT(9);      //CLKXM (1)
        //Receive Clock is an input pin and is driven by the external device
        REGISTER_ACCESS(MCBSP1, MCBSP_PCR_REG) &= ~MASK_BIT(8);        //CLKRM (0)   
        //Receive data sampled on rising edge of CLKR
        REGISTER_ACCESS(MCBSP1, MCBSP_PCR_REG) |= MASK_BIT(0);        //CLKRP   
       
        //Divide the clock down by 95 to get 1MHz
        REGISTER_ACCESS(MCBSP1, MCBSP_SRGR1_REG) |=    0x5F;
       
        //Configure for an input clock  of McBSPi_ICLK
        REGISTER_ACCESS(MCBSP1, MCBSP_PCR_REG) &= ~MASK_BIT(7);        //SCLKME(0)
        REGISTER_ACCESS(MCBSP1, MCBSP_SRGR2_REG) |= MASK_BIT(13);    //CLKSM    (1)
       
        REGISTER_ACCESS(MCBSP1, MCBSP_SPCR2_REG) |= MASK_BIT(7);
       
        //Enable the sample rate generator
        REGISTER_ACCESS(MCBSP1, MCBSP_SPCR2_REG) |= MASK_BIT(6);                                       
        REGISTER_ACCESS(MCBSP1, MCBSP_SPCR1_REG) |= MASK_BIT(0);
        REGISTER_ACCESS(MCBSP1, MCBSP_SPCR2_REG) |= MASK_BIT(0);
       
        for(;;);
       
        return;
       
    }

  • Matt

    The settings for the McBSP are correct - I tested them on a a different board.

    I suspect it may b the GEL files used to setup the device. I've not used CCS4 so I can't help on that just yet.

    Can you successfully step through your code?

      Paul

  • Hey Paul,

    I have tried setting up the same example in CCsv3 and seem to be getting similar results.  The GEL files in ccsv3 seem to be C:\CCStudio_v3.3\boards\omap35xx_3430\gel\sdomap35xx_C64plus.gel for the C64x+ and C:\CCStudio_v3.3\boards\omap35xx_3430\gel\Mistral_Omap35xx_CortexA8.gel for the ARM.  I have noticed that I have to run Clear Memory Map before I can load my app in or else I get "Loader: One or more sections of your program falls into a memory region that is not writable.  These regions will not actually be written to the target.  Check your linker configuration and/or memory map."

     

    On the other side, yep, I can step through and all the memory locations for the MCBSP registers seem to be getting  updated just fine

     

    Thanks again,

    Matt

  • Matt

    I tested your code in CCSV4 and got it to work (from the ARM). I've attached a zip file with the project.

      Paul

    mcbsp_debug.zip
  • Hey Paul,

     

    First off, thank you very much for your help.  I have a few questions about the project that you attached.  I noticed that the target config you used was simply the OMAP3530 which I am assuming I would have to change to the mistral for my config.  I do however, get errors when I attempt to run this on the ARM

     

    Cortex_A8: GEL Output: The code download over AHB is turned OFF.
    Cortex_A8: GEL Output: CPU Reset callback function has fired  
    Cortex_A8: GEL Output: OMAP 32K Watchdog Timer is disable
    Cortex_A8: GEL Output: Setup PRCM clock configuration IIA 
    Cortex_A8: GEL Output:  CORE_DPLL_CLK = 663.771 MHz 
    Cortex_A8: GEL Output:  CORE_CLK = 331.8855 MHz 
    Cortex_A8: GEL Output:  L3_CLK = 165.9427 MHz 
    Cortex_A8: GEL Output: MM01: mDDR Samsung K4X51323PC - 512 Mbit(64MB) on CS0, 4M x 32bit x 4Banks
    Cortex_A8: GEL Output: SDRC initilization for mDDR_Samsung_K4X51323PC completed 
    Cortex_A8: GEL Output: GEL StartUp Complete. 
    Cortex_A8: GEL Output: The code download over AHB is turned OFF.
    Cortex_A8: GEL Output: CPU Reset callback function has fired  
    Cortex_A8: GEL Output: MMU and Cache are OFF. 
    Cortex_A8: GEL Output: The code download over AHB is turned ON.
    Cortex_A8: File Loader: Data verification failed at address 0x80002002 Please verify target memory and memory map.
    Error found during data verification.
    Ensure the linker command file matches the memory map.

    So now I am wondering if a lot of my problems have to do with the "Cortex_A8: GEL Output: MM01: mDDR Samsung K4X51323PC - 512 Mbit(64MB) on CS0, 4M x 32bit x 4Banks" init step.  The board setup I am using is a Micron MT29C2G48MAKLCJI-6 IT but I cannot for the life of me find any gel setup code for that particular chip.  Does this sound like a possibility to you?

     

    Thanks again,

    Matt

  • Matt

    I ran and tested the code on a Mistral OMAP 35x EVM (Rev G) so you should be able to use it and see the same resuts

    The gel file used in the target configuration is ..\..\emulation\gel\omap3530_cortexA.gel. Is this the GEL file you are using?

      Paul

     

  • Hey Paul,

     

    For the C64XP_0 it is ..\..\emulation\gel\omap3430_c64plus.gel and for the Cortex_A8_0 it is ..\..\emulation\gel\omap3530_cortexA.gel with an address of 0xd4011000.  Do the onboard switches of the EVM play any part at all (other than setting JTAG support on).  Current I have SW1 (on the processor modules) set to bit 1 on and all other off and SW4 on the main board set to 3 and 6 on and the rest off.

    But if I run it in the configuration that you sent I get this as an error message popup:

    Trouble Reading Register ETM_ID:
    Error 0x80002004/-1203
    Fatal Error during: Register, Control,
    The DAP access, address 0x000001E4, has returned a SLAVE error.

     

    and this in the output window

    Cortex_A8_0: GEL Output: OMAP 32K Watchdog Timer is disable
    Cortex_A8_0: GEL Output:  Putting DPLL into bypass before proceeding 
    Cortex_A8_0: GEL Output:  Putting CORE DPLL into bypass before proceeding 
    Cortex_A8_0: GEL Output:  Locking CORE DPLL 
    Cortex_A8_0: GEL Output:  PRCM clock configuration IIA setup has been completed 
    Cortex_A8_0: GEL Output:  SystemClock = 19.2 MHz 
    Cortex_A8_0: GEL Output:  DPLL_MULT_VALUE = 242 
    Cortex_A8_0: GEL Output:  DPLL_DIV_VALUE = 13 
    Cortex_A8_0: GEL Output:  CORE_DPLL_CLK = 663.771 MHz 
    Cortex_A8_0: GEL Output:  CORE_CLK = 331.8855 MHz 
    Cortex_A8_0: GEL Output:  L3_CLK = 165.9427 MHz 
    Cortex_A8_0: GEL Output: MM01: mDDR Samsung K4X51323PC - 512 Mbit(64MB) on CS0, 4M x 32bit x 4Banks
    Cortex_A8_0: GEL Output: common_sdram_init() completed 
    Cortex_A8_0: GEL Output: SDRC initilization for mDDR_Samsung_K4X51323PC completed 
    Cortex_A8_0: GEL Output: 19.2MHz clock configuration IIa 
    Cortex_A8_0: GEL Output:      CORTEXA8_CORE_VERSION = 0x411FC083
    Cortex_A8_0: GEL Output:      CORE_REVISION = 0x00100003
    Cortex_A8_0: GEL Output:      IS NOT COMPREHENDED BY THIS GEL FILE
    Cortex_A8_0: Trouble Reading Register ETM_ID: Error 0x80002004/-1203 Fatal Error during: Register, Control,  The DAP access, address 0x000001E4, has returned a SLAVE error. 
    Cortex_A8_0: The GEL callback "OnTargetConnect()" is no longer running atomically
    Cortex_A8_0: GEL: Error while executing OnResetDetected(): target is not connected.

     

  • Hey Paul,

     

    Thought it might be worth mentioning that the current board I am running has been updated to have wince and its boot loader.  Not sure if there is any impact there but I figured I would mention it.

     

    Matt

  • Matt

    I'm not up to speed with WinCE so I cannot comment on if or how that would effect things. One more thing to check though is that the pinmux for the MCBSP1_CLKX (CONTROL_PADCONF_MCBSP1_CLKX) is set to the correct mode. It could be that the WinCE boot loader is modifying the mode to something other than the default.

    For SW1, All off is the configuration I am using. Setting switch 1 (JTAG_EMU0) to "on" causes connection problems for me. Try switching this off. For more details on this see http://processors.wiki.ti.com/index.php/XDS_Target_Connection_Guide#EMU_Pin_Functions

    For SW4, selects the boot mode. With switches 3 & 6 on your are selecting to boot from NAND then USB (See section 25.2.3 Boot Configuration in the TRM for all the options). This should not cause any issues.

      Paul

     

  • Hey Paul,

     

    Well, seems to just be more of the same.  The CONTROL_PADCONF_MCBSP1_CLKX looks right (0x0118010F).  Still cannot seem to run you test app, cannot seem to get by the "Cortex_A8_0: Trouble Reading Register ETM_ID: Error 0x80002004/-1203 Fatal Error during: Register, Control,  The DAP access, address 0x000001E4, has returned a SLAVE error. 
    Cortex_A8_0: GEL: Error while executing OnTargetConnect(): Target failed to read the register ETM_ID." error that pops up and thus it never gets to my break points.".  I have put SW1 back to all off and still seem to have the same errors.

     

    Matt

  • Matt

     

    The CONTROL_PADCONF_MCBSP1_CLKX is not correct. The MCBSP1_CLKX pin is controlled by the lower 16 bits [15:0] and the lowest 3 bits [2:0] control the mode of the pin. Currently you have these bits set to 0x7 which selects safe_mode. You need to the mode to 0x0 which will select mcbsp1_clkx. The upper 16 bits control the uart3_rts_rctx pin.

    Using CCS V4, can you launch the TI Debugger (Target>Launch TI Debugger) and connect to the ARM (right click on the ARM "Thread [main]" and select connect)?

    Previously I said that the boot mode switches should not cause issues which generally is true. However, it is possible that the boot loader you are using is affecting your ability to connect. As a test, you should try setting to boot mode switch so that the boat loader is not run.

      Paul


  • Hey Paul,

     

    Well, that seemed to do it.  I now have a free running clock on my clkx pin.  Thank you very much. One quick thing, is there a easy way to put the entire chip in mode 0?

    Thanks for all your help,

    Matt

  • Matt

    There is no way to change modes other than writing to the padconf registers. The reset mode for each pin can be found the in the device data manual.

      Paul

  • No worries.

    Thanks again for the MCBSP help.  Any chance you have experience with DMA and the MCBSP.  I now am having a bit of a problem with that...

     

    Matt

  • Matt

    I've not worked with the DMA before, but it sounds like an opportunity to do so. What is the problem?

      Paul

  • Hey Paul,

     

    Well, it goes like this.  Once I had the MCBSP up and running I configured it to receive a frame of length X from an external source device.  I set the thresh1 of the BSP to x-1 and enabled the DMA receive events.  Prior to all this, I setup the DMA as follows.  Now the interesting thing is that in CCSv4 I can see data coming in on the DRR of the MCBSP (simple setting the automatic refresh and watching that memory address).  I can also see the two channel enable bits of channel 11 and 12 (in DMA4_CCRi) toggling back and forth (i.e. channel 11 enabled then channel 12) so it looks like something is triggering them (which I assume is the MCBSP1 RX Event) but I do not seem to be getting any data in my ping pong arrays (which are just unsigned int pingData[X]).  Any Ideas?

     

    Thanks,

    Matt

    #define DMA_CHANNEL_ACCESS(root, dma_channel) *(devPtr)(root + (0x60 * dma_channel))

    void initSDMA()
    {   
        DMA_CHANNEL_ACCESS(DMA_CCRi_REG, 11) = 0;
        DMA_CHANNEL_ACCESS(DMA_CCRi_REG, 11) |= 0x20;           //Frame mode
        DMA_CHANNEL_ACCESS(DMA_CCRi_REG, 11) |= 0x4000;      //Destination Post Addressing
        DMA_CHANNEL_ACCESS(DMA_CCRi_REG, 11) |= 0x80000;      //MCBSP1 Rx Event
        DMA_CHANNEL_ACCESS(DMA_CCRi_REG, 11) |= 0x1000000;      //Source Triggered
       
        DMA_CHANNEL_ACCESS(DMA_CSDPi_REG, 11) = 0;
        DMA_CHANNEL_ACCESS(DMA_CSDPi_REG, 11) |= 0x2;         //32 bits per element
        DMA_CHANNEL_ACCESS(DMA_CSDPi_REG, 11) |= 0x10000;      //write posted
       
        //Set the number of elements per frame
        DMA_CHANNEL_ACCESS(DMA_CENi_REG, 11) = 0;
        DMA_CHANNEL_ACCESS(DMA_CENi_REG, 11) = 0xXX         //X elements per frame
       
        //Set the number of elements per frame
        DMA_CHANNEL_ACCESS(DMA_CFNi_REG, 11) = 0;
        DMA_CHANNEL_ACCESS(DMA_CFNi_REG, 11) = 0x1;          //1 frame per block

        //set the read start address
        DMA_CHANNEL_ACCESS(DMA_CSSAi_REG, 11) = 0;
        DMA_CHANNEL_ACCESS(DMA_CSSAi_REG, 11) = 0x48074000;
       
        //set the write start address
        DMA_CHANNEL_ACCESS(DMA_CDSAi_REG, 11) = 0;
        DMA_CHANNEL_ACCESS(DMA_CDSAi_REG, 11) = (unsigned int)&pingData[0];
           
        //Set the destination increment
        DMA_CHANNEL_ACCESS(DMA_CDELi_REG, 11) = 0;
        DMA_CHANNEL_ACCESS(DMA_CDELi_REG, 11) = 0x1;

        //DMA_CHANNEL_ACCESS(DMA_CICRi_REG, 11) = 0x8;   
       
        //Link to channel 12
        DMA_CHANNEL_ACCESS(DMA_CLNK_CTRLi_REG, 11) = 0x800C;
       

        //Channel 12   
        DMA_CHANNEL_ACCESS(DMA_CCRi_REG, 12) = 0;
        DMA_CHANNEL_ACCESS(DMA_CCRi_REG, 12) |= 0x20;           //Frame mode
        DMA_CHANNEL_ACCESS(DMA_CCRi_REG, 12) |= 0x4000;       //Destination Post Addressing
        DMA_CHANNEL_ACCESS(DMA_CCRi_REG, 12) |= 0x80000;      //MCBSP1 Rx Event
        DMA_CHANNEL_ACCESS(DMA_CCRi_REG, 12) |= 0x1000000;      //Source Triggered
       
        DMA_CHANNEL_ACCESS(DMA_CSDPi_REG, 12) = 0;
        DMA_CHANNEL_ACCESS(DMA_CSDPi_REG, 12) |= 0x2;          //32 bits per element
        DMA_CHANNEL_ACCESS(DMA_CSDPi_REG, 12) |= 0x10000;      //write posted
       
        //Set the number of elements per frame
        DMA_CHANNEL_ACCESS(DMA_CENi_REG, 12) = 0;
        DMA_CHANNEL_ACCESS(DMA_CENi_REG, 12) = 0xXX;          //X elements per frame
       
        //Set the number of elements per frame
        DMA_CHANNEL_ACCESS(DMA_CFNi_REG, 12) = 0;
        DMA_CHANNEL_ACCESS(DMA_CFNi_REG, 12) = 0x1;          //1 frame per block

        //set the read start address
        DMA_CHANNEL_ACCESS(DMA_CSSAi_REG, 12) = 0;
        DMA_CHANNEL_ACCESS(DMA_CSSAi_REG, 12) = 0x48074000;
       
        //set the write start address
        DMA_CHANNEL_ACCESS(DMA_CDSAi_REG, 12) = 0;
        DMA_CHANNEL_ACCESS(DMA_CDSAi_REG, 12) = (unsigned int)&pongData[0];
           
        //Set the destination increment
        DMA_CHANNEL_ACCESS(DMA_CDELi_REG, 12) = 0;
        DMA_CHANNEL_ACCESS(DMA_CDELi_REG, 12) = 0x1;           

        //DMA_CHANNEL_ACCESS(DMA_CICRi_REG, 12) = 0x8;     

        //Link to channel 11
        DMA_CHANNEL_ACCESS(DMA_CLNK_CTRLi_REG, 12) = 0x800B;

        //Enable DMA
        DMA_CHANNEL_ACCESS(DMA_CCRi_REG, 11) |= 0x80;
       
    }

  • Matt

    Sorry for the lack of updates. I've been having computer issues.

    Do you still have the problem?

      Paul

  • Hey Paul,

     

    Sorry to hear about your PC problems.

    Unfortunately, I am still having the problem.  I have stepped back for a few days, the frustration was getting to me ;)

  • Matt

    Apologies for the delay in getting back to you.

    I wrote some code to implement a buffer scheme similar to yours. The DMA settings are very similar, only varying due to buffer locations and such. With these settings the DMA transfers worked as expected. Here are the register configurations:

    // Channel 11 settings:

    CCRI      0x01084020    // Control register (SRC_TRIG + MCBSP2_RX + DEST_POST_INC + SRC_CONST + FS)
    CSDP      0x00010002    // SRC/DEST parameters (Write_Posted + 32bits Scalar)
    CEN       0x00000010    // 16 Elements in a frame
    CFN       0x00000001    //  1 Frame in a block
    CSSA      0x48074000    // Source address  (McBSP1 DRR)

    CDSA      0x80001EBC    // Destination address (Array in memory)
    CSEL      0x00000001    // Channel Source index element
    CDEL      0x00000001    // Channel destination index element
    CLNK_CTRL 0x0000800C    // Enable link, Next Channel = 12

     

    // Channel 12 settings:
    CCRI      0x01084020    //
    CSDP      0x00010002    //
    CEN       0x00000010    // 16 Elements in a frame
    CFN       0x00000001    //  1 Frame in a block
    CSSA      0x48074000    // Source address  (McBSP1 DRR)
    CDSA      0x80001EFC    // Destination address (Array in memory)
    CSEL      0x00000001    // Channel Source index element
    CDEL      0x00000001    // Channel destination index element
    CLNK_CTRL 0x0000800B    // Enable link, Next Channel = 11

     

    All that's left is to enable one of the channels via the CCRi.ENABLE bit.

    The Mcbsp1 THRSH1 is set to 0xE.

    I can attach my code if that would be helpful? Just need to tidy it up a bit first.

      Paul

     

     

     

     

     

  • Matt

    Attached is an example CCSV4 project which demonstrates the RX DMA using 3 rotating buffers.

    Please let me know if you have any questions.

      Paul

    MCBSP_RX_DMA_1.zip
  • Hi Paul,

    Is it possible that you can help me with an EDMA issue?  (OMAP3530 EVM)
    I posted the question in this link:
    http://e2e.ti.com/support/dsp/davinci_digital_media_processors/f/99/p/6905/200908.aspx#200908
     
    I orginally hoped to move data from McBSP2 via EDMA channel to DSP, but stuck
    in a simple memory copy.

    Juliann

     

     

  • Juliann

    Unfortunately I'm not the best person to provide a speedy answer when it comes to EDMA. Brad looks like he's already responding.

    Best regards

      Paul

  • Pau,

        When i try to use your sample program Loopback or McBSP_RX_DMA on BeagleBoard, program always collapsed at the first line and give me an error as

     

    ###             Program received signal SIGSEGV, Segmentation fault.
                        0x000084ec in dmaSetCsdp ()

      ###

     How to solve this problem and make it run?

    Fatih

  • Fatih

    The examples I provided are stand alone but, based on the error message, it looks like you are trying to use it with Linux running which will not work.

    There are some examples in the Linux PSP directiory .../src/examples/audio which may be useful.

      Paul

     

  • Paul

    How can i use your sample code, how can i run it on which platfrom? and I am using Angstrom or Ubuntu on Beagleboard, how can i use the McBSP with linux?

     

    Fozay

  • Under Linux you would have to write a driver that uses McBSP.  What kind of device are you connecting? If it is an audio codec, there are existing audio drivers that use McBSP already in the Linux kernel. That could be a good start for sample code.

    Steve K.

  • Steve

    Nope unfortunately i will connect it a video encoder device. Even if you have audio codec driver might be useful. 

    Here it comes a different question: How can i run the examples code? I mean what should be the platform or where can i run it?

    Can you descibe it step by step.

    I didnt understand the standalone concept.

     

    Fozay 

  • Paul,

    I came across your thread with Matt when I googled the  OMAP3530 "Trouble Reading Register ETM_ID:" issue that Matt encountered.  I'm seeing the same error on a custom target that consists of an OMAP3530 running Greenhill's Integrity and an FPGA.  However, in my case, the error is intermittent and I have routinely been manually connecting the ARM after launching  Target->Launch TI Debugger  in non-project mode.

    I don't see the problem on either a Mistral EVM or a second custom target that has a more recent boot loader, so I suspect a conflict between an OMAP pin and a pin on the FPGA (primarily, Mc BSP, GPIO and GPMC interfaces).

    I was wondering if you could help me narrow the search by suggesting possible causes of the error message?

    Thanks in advance..

  • Bob

     

    Have you tried the more recent boot loader in the intermittent custom target?

     

    Are the any of the JTAG signals shared such that there is a possibility of contention with another driver?

     

    On a similar note, could one of the signals be floating?

     

      Paul

     

  • Paul,

    Your example works well.......Any chance there exists an equivalent example for DMA'ing into the transmitter. i am currently trying to set that up. My application is required to transmit messages over the MCBSP1 ranging in size from 5 bytes to 16384 bytes. The element size is 32 bits. I am attaching the code. Thanks for your help in advance.

     

    Michael

     

    void mcbsp_dma_write(  UINT MHALphysMemWriteLocation, UINT   byteCount )  
    {
        UINT numFrames = 0;
        UINT RegVal = 0;
        UINT statusReadCnt = 0;
       

         MCBSPdmaAccessState = D_DMA_ACCESS_STATE_WRITE;

        mcbspSetTxThresh(MY_MCBSP, 8);
        mcbspEnableTxDma(MY_MCBSP);

        *(UINT*)pDMA4_IRQSTATUS_L(CHAN12) = 1;         
       
        *(UINT*)pDMA4_CSDP_i(CHAN12) = 0x00000002;

        // init CEN0 register to passed in byte count
        // thsi is the number of elements per frame   
        *(UINT*)pDMA4_CEN_i(CHAN12) = 8;
     
        numFrames = ( byteCount  / 32 );
        if (byteCount % 32)
                 numFrames++;

        // init CFN0 register to 1 frame per block  
        *(UINT*)pDMA4_CFN_i(CHAN12) = (numFrames);

        // init CSSA0 register to passed in data buffer  
        *(UINT*)pDMA4_CSSA_i(CHAN12) = MHALphysMemWriteLocation;

        // init CDSA0 register to MHAL data address in the FPGA
        *(UINT*)pDMA4_CDSA_i(CHAN12) = D_MCBSP1LP_DXR_REG_ADDR;
        //*(UINT*)pDMA4_CDSA_i(CHAN12) = 0x80500000;

        //*(UINT*)pDMA4_CCR_i(CHAN12) = 0x01005020;
        *(UINT*)pDMA4_CCR_i(CHAN12) = 0x01001020;
        //*(UINT*)pDMA4_CCR_i(CHAN12) = 0x0100103f;

        // init CSE0 register to 1
        *(UINT*)pDMA4_CSEI_i(CHAN12) = 1;

        // init CSF0 register to 1
        *(UINT*)pDMA4_CSFI_i(CHAN12) = 0;

        // init CDE0 register to 1
        *(UINT*)pDMA4_CDEI_i(CHAN12) = 1;

        // init CDF0 register to 1
        *(UINT*)pDMA4_CDFI_i(CHAN12) = 0;

        mcbspRemoveResetTx(MY_MCBSP);

        //*(UINT*)pDMA4_IRQENABLE_L(0) = 0x0001;

        *(UINT*)pDMA4_CCR_i(CHAN12) |= DMA4_CCR0_ENABLE_BIT_MASK ;

        *(UINT*)pDMA4_CICR_i(CHAN12) = 0 ;

        statusReadCnt = 0;
        RegVal = *(UINT*)pDMA4_CSR_i(CHAN12);
        while ( ( ( RegVal & 0x20 ) != 0x20 ) && ( statusReadCnt < 60 ) )
        {
              //CSRRegVal[statusReadCnt] = *(UINT*)pDMA4_CSR_i(D_CHAN0_DMA);
             RegVal = *(UINT*)pDMA4_CSR_i(CHAN12);
            statusReadCnt++;
        }
       
        *(UINT*)pDMA4_CSR_i(CHAN12) |= RegVal;

        *(USHORT*)FPGA_MCBSP_BUFF_WRITE_DONE_REGISTER = (USHORT)1;

        mcbspResetTx(MY_MCBSP);

        return;

    }

  • Michael

    I didn't have a TX example so I modified the RX example to be a TX/RX DMA example. The source code is attached and can be used with the header and lib files from the original example.

      Paul

     

  • Paul,

    You helped me a great deal with the MCBSP issues I was having. I am hoping to tap into you expertise for another problem I am having. It is with the GPMC. I am using the GPMC to do data exchanges with a FPGA. The DMA transfers are working with the FPGA.....They just seem to be slow. The reason for the latency is not that the data is getting to the FPGA slowly....it is that he interrupt from the DMA controller is coming Here are the detail:

    I am using DMA with bursting turned on

    the fpga is mapped and being accessed with chip select 4 to do the dma transfers

    The DMA transmit to the fpga is 32 bytes

    I am attaching the source which executes the dma write to the fpga

    Thanks again

    Michael

     

     

    Boolean writeBurst(void)
    {
        UINT4  numFrames = 0;
        //UINT2 RegisterValue = 0;
        UINT4   byteCount = 32;


         f_GPMCdmaAccessState  = D_DMA_ACCESS_STATE_WRITE;

        *(UINT4*)pDMA4_IRQSTATUS_L(D_CHAN0_DMA) = 1;  

        *(UINT4*)pDMA4_CSDP_i(D_CHAN0_DMA) = 0xa141;

        *(UINT4*)pDMA4_CICR_i(D_CHAN0_DMA) = 0x1d22;

        // init CEN0 register to passed in byte count
        // thsi is the number of elements per frame   
        *(UINT4*)pDMA4_CEN_i(D_CHAN0_DMA) = 16;

        // calculate the number of frames from the byte count

        numFrames = ( byteCount / 32 );
        if (byteCount % 32)
        numFrames++;

        // init CFN0 register to num of frames

        *(UINT4*)pDMA4_CFN_i(D_CHAN0_DMA) = (numFrames);  

        // init CSSA0 register to passed in data buffer  
        *(UINT4*)pDMA4_CSSA_i(D_CHAN0_DMA) = f_GPMClastPhyMemDMAWriteLocn;

        // init CDSA0 register to data address in the FPGA
        *(UINT4*)pDMA4_CDSA_i(D_CHAN0_DMA) = FPGA_DATA_BASE;

        *(UINT4*)pDMA4_CCR_i(D_CHAN0_DMA) = 0x0104a000;

        // init CSE0 register to 1
        *(UINT4*)pDMA4_CSEI_i(D_CHAN0_DMA) = 1;

        // init CSF0 register to 1
        *(UINT4*)pDMA4_CSFI_i(D_CHAN0_DMA) = 1;

        // init CDE0 register to 1
        *(UINT4*)pDMA4_CDEI_i(D_CHAN0_DMA) = 1;

        // init CDF0 register to 1
        *(UINT4*)pDMA4_CDFI_i(D_CHAN0_DMA) = 1;

        *(UINT4*)pDMA4_IRQENABLE_L(0) = 0x0001;

        *(UINT4*)pDMA4_CCR_i(D_CHAN0_DMA) |= DMA4_CCR0_ENABLE_BIT_MASK;

        return true;
    }

     

     

  • Michael

    Other would be better suited to answer this question in a timely manner. Best thing is to start a new thread on the subject.

      Paul

  • Paul,

    I am new to your website....I do not see how to start a new thread.

    Can you give me some direction?

    Michael