Hyperlink between two K2E boards

dpa

Other Parts Discussed in Thread: 66AK2E05, AM5K2E04

Hi,

My goal is to use Hyperlink to connect two SOCs on A15 side (in two 66AK2E05 SOCs at the moment, in two AM5K2E04 in the future) on the same board. In order to test the feasibility I have started by testing the MCSDK Hyperlink example compiled for ARM. With internal loopback enabled, the test is successful.

But when I am trying to perform an external Loopback (RX to TX) on one single board, the example is blocked on the wait for Lane 0 Signal Detect State to go high (see also the begining of the log below).

2 questions:

1) Since my test is first a board to board test, how is it possible to generate the .c file for serdes config with 1.25GBps? I want to use the minimal Speed for this particular test.

2) What do I need to check to investigate this issue? Is it even possible the way I want to do? DO you have any tips?

Version #: 0x02010004; string HYPLNK LLD Revision: 02.01.00.04:Dec 17 2015:12:04:44
About to do system setup (PLL, PSC, and DDR)
Power domain is already enabled.  You probably re-ran without device reset (which is OK)
Constructed SERDES configs: PLL=0x00000228; RX=0x0046c495; TX=0x000ccf95
system setup worked
About to set up HyperLink Peripheral
============================
Hyperlink Testing Port 0 
============================
============== begin registers before initialization ===========
Revision register contents:
  Raw    = 0x4e902101
  Scheme = 1
  BU     = 0
  Func   = 0x0e90
  RTL    = 4
  cust   = 0
  revMaj = 1
  revMin = 1
Status register contents:
  Raw        = 0x00002004
  swidthin   = 0
  swidthout  = 0
  serialHalt = 1
  pllUnlock  = 0
  rPend      = 0
  iFlow      = 0
  oFlow      = 0
  rError     = 0
  lError     = 0
  nfEmpty3   = 0
  nfEmpty2   = 0
  nfEmpty1   = 0
  nfEmpty0   = 0
  sPend      = 1
  mPend      = 0
  link       = 0
Link status register contents:
  Raw       = 0x00000000
  txPlsReq  = 0
  txPlsAck  = 0
  txPmReq   = 0
  txRSync   = 0
  txPlsOK   = 0
  txPhyEn   = 0
  txFlowSts = 0
  rxPlsReq  = 0
  rxPlsAck  = 0
  rxPmReq   = 0
  rxLSync   = 0
  rxPhyEn   = 0
  rxPhyPol  = 0
Control register contents:
  Raw             = 0x00006004
  intLocal        = 1
  statusIntEnable = 1
  statusIntVec    = 0
  int2cfg         = 0
  serialStop      = 1
  iLoop           = 0
  reset           = 0
Control register contents:
  Raw        = 0x00000000
  sglErrCor  = 0
  dblErrDet  = 0
============== end registers before initialization ===========

over 9 years ago

0 Raja over 9 years ago

TI__Guru* 81335 points

Welcome to the TI E2E forum. I hope you will find many good answers here and in the TI.com documents and in the TI Wiki Pages (for processor issues). Be sure to search those for helpful information and to browse for the questions others may have asked on similar topics (e2e.ti.com). Please read all the links below my signature.

We will get back to you on the above query shortly. Thank you for your patience.

0 Ganapathi Dhandapani95 over 9 years ago

TI__Mastermind 28085 points

Hi,

For my understanding, ARM and DSP Hyperlink examples are using same address mapping and configuration. Please refer the "hyplnkLLDCfg.h" to change the Hyperlink serdes configuration. This file contains the definitions that are used to configure the Hyperlink peripheral, such as selecting the serial speed and loopbacks.

File Path: \ti\pdk_keystone2_3_01_04_07\packages\ti\drv\hyplnk\example\common\hyplnkLLDCfg.h

Thanks,

0 dpa over 9 years ago in reply to Ganapathi Dhandapani95

Expert 1010 points

Hi,

Thanks for the answer.

I already saw the hyplnkLLDCfg.h and changed the configuration to 1.25GBps but this speed is defined in code but not supported. There are some auto generated .c files for some combinations (for example csl_wiz8_sb_refclk312p5MHz_20bit_6p25Gbps.c) but not for the configuration I want to use. How can I generate one of them for 1.25GBps?

The speed defined above is just for test purpose. My main concern is to determine if I can have an issue with my configuration or by the compilation for example before investigating further into hardware. I am suspecting an hardware issue since the example code is blocked by CSL_SerdesWaitForSigDet in CSL_SerdesLaneEnable_Lane_Init_RX (in csl_serdes.h) but I want to be sure.

Why can I test to determine the source of the problem?

At the moment, the config is set without internal loopback, reference clock to 312.5MHz, speed to default 3.125GBps and it does not work.

I have read some similar threads like this one : e2e.ti.com/.../364097
but it did not help me.

0 dpa over 9 years ago in reply to Ganapathi Dhandapani95

Expert 1010 points

Hi,
I managed to make the example work for ARM (HW Problem) but the round-trip delay is always null.
I then noticed that the example is using hyplnkExampleReadTime like this:

static inline uint64_t hyplnkExampleReadTime ()
{
#ifdef __ARMv7
return 0;
#else
uint32_t low = TSCL;
uint32_t high = TSCH;
return _itoll(high,low);
#endif
}

How can I get the time on ARM for a round-trip as defined in this example?

I tried with (unsigned long long)clock(); but it does not seem to work well.

0 Ganapathi Dhandapani95 over 9 years ago in reply to dpa

TI__Mastermind 28085 points

Hi,

I do not test the hyperlink example on ARM core. I will check with my team and get back to you.

Thanks,

0 dpa over 9 years ago in reply to Ganapathi Dhandapani95

Expert 1010 points

Hi,

Do you have some news for this topic?
I am facing this problem each time I want to measure a time difference enough precisely.

Regards

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Hyperlink between two K2E boards