Hi,
I am working on AM4379 based design.
I have to do the power analysis of my architecture.
Anyone can share the link of AM43xx Power Consumption Summary application report.
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Hi,
I am working on AM4379 based design.
I have to do the power analysis of my architecture.
Anyone can share the link of AM43xx Power Consumption Summary application report.
Hi,
I have one doubt in am437x design that is in giabit ethernet phy chip design.
As per datasheet of KSZ9031RNXCA (phy chip) AVDDl,DVDDL and AVDDL_PLL maximum voltage is 1.8V.
But in the design applied 3.3V through P channel mosfet.
I know it is working fine in EVM .
Is there any reason to give 3.3V. Below is the design
Dear Biser,
Can you share the latest PET for Device rev PG2.1.
Because Device rev PG1.1 support up to 600MHz only.
I need the PET for 1GHz.