OMAP3 McSPI Turbo Mode Example?

Bernie Thompson TI

Other Parts Discussed in Thread: AM3517, SYSCONFIG, OMAP3530, DM3730

I have an application where the OMAP3 needs to be an SPI master and hold the CS signal low for multiple words, it is actually the same issue as in this thread, however beyond that I am curious about the turbo mode described in section 19.5.2.5.3 of SPRU98d. The turbo mode describes holding the CS low, though I don't think it will solve this particular customer's problem, he is asking how to activate and what it is for. My impression is that it is only a performance increasing setting, it seems to lock the incoming shift register to a single channel's receive register, so that both can be filled up before servicing, is that an accurate description?

When the turbo bit is set in this case the SPI stops outputting messages, so I am trying to find out why that could happen, do we have any example configurations or code that use the McSPI turbo mode? It looks like it should be as easy as having just a single channel in use, setting the single bit and than the turbo bit.

over 15 years ago

0 PaulM over 15 years ago

TI__Mastermind 28055 points

Bernie

I am currently working on setting up examples for the AM35x SPI wiki so hopefully there will be example code content there soon.

Until then here a quick example of code I used to transfer 16 words with the CS low for all 16 words.

It's not pretty (yet) but it does the job.

/*
Simple example to transmit incrementing data on McSpi1 with manually controlled CS
Simple diagnostics will be output via the UART
*/

// Includes from the Logic bsl
#include "types.h"
#include "evmam35xx.h"
#include "evmam35xx_gpio.h"
#include "evmam35xx_i2c.h"
#include "evmam35xx_timer.h"

// Includes specific to McSpi:
#include "AM35xx_MCSPI.h"

// Local defines which are not included in bsl headers.
#define CM_ICLKEN1_CORE_EN_SPI1    (0x40000)
#define CM_FCLKEN1_CORE_EN_SPI1    (0x40000)

int main (void)
{

    uint32_t tx_data, mcspi_base, tmp1, tmp;

/////////////////////////////////////////////////////////////
// Utilize the AM3517 EVM BSP software to initialize the
// system and other peripherals.
//

EVMAM35XX_init();
debug_print_init();
USTIMER_init();

mcspi_base = SPI1_REG_BASE; // Select McSpi1

// Enable clocks
SETBIT_REGL(CM_ICLKEN1_CORE, CM_ICLKEN1_CORE_EN_SPI1);   // Turn on the interface clock
SETBIT_REGL(CM_FCLKEN1_CORE, CM_FCLKEN1_CORE_EN_SPI1);   // Turn on the function clock

debug_print("Configuring McSpi1\r\n");
SETBIT_REGL(mcspi_base + SPI_SYSCONFIG, SPI_SYSCONFIG_SOFTRESET);       // Initiate a soft reset

while (!CHKBIT_REGL(mcspi_base+SPI_SYSSTATUS, SPI_SYSSTATUS_RESETDONE)) {
     debug_print("Waiting... SPI_SYSSTATUS   = 0x%08x\r\n", IN_REGL(mcspi_base+SPI_SYSSTATUS)); // Wait for reset to complete
}
debug_print("Reset Done\r\n");
CLRBIT_REGL(mcspi_base + SPI_CH0CONF, SPI_CONF_IS);     // Set somi pin to receive mode
CLRBIT_REGL(mcspi_base + SPI_CH0CONF, SPI_CONF_DPE1);   // Set simo pin to transmit mode
SETBIT_REGL(mcspi_base + SPI_CH0CONF, SPI_CONF_DPE0);   //   (as previous line)
SETBIT_REGL(mcspi_base + SPI_CH0CONF, SPI_CONF_TRM_1); // Set TX only mode
CLRBIT_REGL(mcspi_base + SPI_CH0CONF, SPI_CONF_TRM_0); //   (as above)
SETBIT_REGL(mcspi_base + SPI_CH0CONF, SPI_CONF_WL_0);   // Select word size
SETBIT_REGL(mcspi_base + SPI_CH0CONF, SPI_CONF_WL_1);   //     "
SETBIT_REGL(mcspi_base + SPI_CH0CONF, SPI_CONF_WL_2);   //     "
CLRBIT_REGL(mcspi_base + SPI_CH0CONF, SPI_CONF_WL_3);   //     "
CLRBIT_REGL(mcspi_base + SPI_CH0CONF, SPI_CONF_WL_4);   //     "
SETBIT_REGL(mcspi_base + SPI_CH0CONF, SPI_CONF_EPOL);   // CS active low
SETBIT_REGL(mcspi_base + SPI_CH0CONF, SPI_CONF_CLKD_0); // Set clock divider
SETBIT_REGL(mcspi_base + SPI_CH0CONF, SPI_CONF_CLKD_1); //     "
SETBIT_REGL(mcspi_base + SPI_CH0CONF, SPI_CONF_CLKD_2); //     "
CLRBIT_REGL(mcspi_base + SPI_CH0CONF, SPI_CONF_CLKD_3); //     "
CLRBIT_REGL(mcspi_base + SPI_CH0CONF, SPI_CONF_POL);    // CLK inactive low
CLRBIT_REGL(mcspi_base + SPI_CH0CONF, SPI_CONF_PHA);    // Odd edges sample data
CLRBIT_REGL(mcspi_base + SPI_MODULCTRL, SPI_MODULCTRL_MS); // Provide the clock in master mode

tx_data = 0;

SETBIT_REGL(mcspi_base + SPI_MODULCTRL, SPI_MODULCTRL_SINGLE);     // Single mode
SETBIT_REGL(mcspi_base + SPI_CH0CTRL, SPI_CTRL_EN);                // Activate channel
SETBIT_REGL(mcspi_base+SPI_IRQSTATUS, SPI_IRQSTATUS_TX0_EMPTY);    // Clear TX0_EMPTY
while (1) {
    debug_print("Transmitting data\r\n");
    SETBIT_REGL(mcspi_base + SPI_CH0CTRL, SPI_CTRL_EN);              // Activate channel
    SETBIT_REGL(mcspi_base+SPI_IRQSTATUS, SPI_IRQSTATUS_TX0_EMPTY); // Clear TX0_EMPTY
    SETBIT_REGL(mcspi_base + SPI_CH0CONF, SPI_CONF_FORCE);
    // send 16 words
    for (tmp=0; tmp<16; tmp++) {
      OUT_REGL(mcspi_base + SPI_TX0, tx_data++);                   // Send word
      while (!CHKBIT_REGL(mcspi_base+SPI_IRQSTATUS, SPI_IRQSTATUS_TX0_EMPTY)) {}
      SETBIT_REGL(mcspi_base+SPI_IRQSTATUS, SPI_IRQSTATUS_TX0_EMPTY); // Clear TX0_EMPTY
    }
    CLRBIT_REGL(mcspi_base + SPI_CH0CONF, SPI_CONF_FORCE);
    CLRBIT_REGL(mcspi_base + SPI_CH0CTRL, SPI_CTRL_EN);         // DE-activate channel
    debug_print("Transmission done\r\n\n");
}
}

BRs

Paul

0 Bernie Thompson TI over 15 years ago in reply to PaulM

TI__Mastermind 41665 points

This looks like a good example of using the FORCE bit to have the CS asserted over multiple words (using the force functionality does work for the customer), though I do not see the TURBO bit being set here, do you have any examples of the turbo mode being used?

If you have a test setup to verify this code, could you try running it with setting the TURBO bit to see if it still works? If I can tell the customer we have a working test case for the turbo mode, and even better if I can provide the source that is known to work, that would help a lot.

0 PaulM over 15 years ago in reply to Bernie Thompson TI

TI__Mastermind 28055 points

The example code provide is setup as TX only. Setting the TURBO mode did not have any effect on the operation - appears to be a RX only setting.

There's not much information on TURBO operational specifics so I'll setup an example to test the mode.

I'll try and get this to you later today.

0 PaulM over 15 years ago in reply to PaulM

TI__Mastermind 28055 points

I've contacted the IP owner but I am still waiting to hear back.

However, as a result of the test I did here is what I have learned:

In non TURBO mode, transfers will stop once the receive register contains a word. Once the word has been read from the receive register a new transfer will be started and the process repeated.

TURBO mode improves the throughput of the SPI interface by allowing transfers until the shift register and the receiver register are full.

In both TURBO and non TURBO modes the CSn line is toggled between words.

TURBO mode can only be used when the MCSPI module is configured as a receive only master or transmit/receive master.

TURBO can be used with DMA, FIFO, and Polling methodologies.

Here's some example code:

/*

Simple example to receive data on McSpi1
Simple diagnostics will be output via the UART

This program shows the McSPI module configured as Master, RX only.
It can operate in one of three modes:

1. Recieve only
2. Receive only with turbo
3. Receive only with FIFO
4. Receive only with FIFO & TURBO

The mode can be selected by setting/resetting the turbo_mode & rx_fifo variables

The code is based on the flow charts found in the AM35x Technical Reference Manual

*/

// Includes from the logic bsl
#include "types.h"
#include "evmam35xx.h"
#include "evmam35xx_gpio.h"
#include "evmam35xx_i2c.h"
#include "evmam35xx_timer.h"

// Includes specific to McSpi:
#include "AM35xx_MCSPI.h"

// Local defines which are not included in bsl headers.
#define CM_ICLKEN1_CORE_EN_SPI1    (0x40000)
#define CM_FCLKEN1_CORE_EN_SPI1    (0x40000)

uint32_t PSUEDO_MCSPI_ISR (uint32_t);

uint32_t max_words, read_count, last, turbo_mode;

int main (void)
{

uint32_t mcspi_base, tmp, rx_data, rx_fifo;

/////////////////////////////////////////////////////////////
// Select which mode for operation.
//
turbo_mode = 1;   // Enable turbo mode
rx_fifo    = 1;   // Enable receive FIFO

/////////////////////////////////////////////////////////////
// Utilize the AM3517 EVM BSP software to initialize the
// system and other peripherals.
//

EVMAM35XX_init();
debug_print_init();
USTIMER_init();

/////////////////////////////////////////////////////////////
// Configure the McSPI module

mcspi_base = SPI1_REG_BASE; // Select McSpi1

// Enable clocks
SETBIT_REGL(CM_ICLKEN1_CORE, CM_ICLKEN1_CORE_EN_SPI1);   // Turn on the interface clock
SETBIT_REGL(CM_FCLKEN1_CORE, CM_FCLKEN1_CORE_EN_SPI1);   // Turn on the function clock

debug_print("Configuring McSpi1\r\n");
SETBIT_REGL(mcspi_base + SPI_SYSCONFIG, SPI_SYSCONFIG_SOFTRESET);       // Initiate a soft reset

while (!CHKBIT_REGL(mcspi_base+SPI_SYSSTATUS, SPI_SYSSTATUS_RESETDONE)) {
     debug_print("Waiting... SPI_SYSSTATUS   = 0x%08x\r\n", IN_REGL(mcspi_base+SPI_SYSSTATUS)); // Wait for reset to complete
}
debug_print("Reset Done\r\n");
CLRBIT_REGL(mcspi_base + SPI_CH0CONF, SPI_CONF_IS);        // Set somi pin to receive mode
CLRBIT_REGL(mcspi_base + SPI_CH0CONF, SPI_CONF_DPE1);      // Set simo pin to transmit mode
SETBIT_REGL(mcspi_base + SPI_CH0CONF, SPI_CONF_DPE0);      //   (as previous line)
CLRBIT_REGL(mcspi_base + SPI_CH0CONF, SPI_CONF_TRM_1);     // Set RX only mode
SETBIT_REGL(mcspi_base + SPI_CH0CONF, SPI_CONF_TRM_0);     //   (as above)
SETBIT_REGL(mcspi_base + SPI_CH0CONF, SPI_CONF_WL_0);      // Select word size
SETBIT_REGL(mcspi_base + SPI_CH0CONF, SPI_CONF_WL_1);      //     "
SETBIT_REGL(mcspi_base + SPI_CH0CONF, SPI_CONF_WL_2);      //     "
CLRBIT_REGL(mcspi_base + SPI_CH0CONF, SPI_CONF_WL_3);      //     "
CLRBIT_REGL(mcspi_base + SPI_CH0CONF, SPI_CONF_WL_4);      //     "
SETBIT_REGL(mcspi_base + SPI_CH0CONF, SPI_CONF_EPOL);      // CS active low
CLRBIT_REGL(mcspi_base + SPI_CH0CONF, SPI_CONF_CLKD_0);    // Set clock divider
SETBIT_REGL(mcspi_base + SPI_CH0CONF, SPI_CONF_CLKD_1);    //     "
CLRBIT_REGL(mcspi_base + SPI_CH0CONF, SPI_CONF_CLKD_2);    //     "
CLRBIT_REGL(mcspi_base + SPI_CH0CONF, SPI_CONF_CLKD_3);    //     "
CLRBIT_REGL(mcspi_base + SPI_CH0CONF, SPI_CONF_POL);       // CLK inactive low
CLRBIT_REGL(mcspi_base + SPI_CH0CONF, SPI_CONF_PHA);       // Odd edges sample data
CLRBIT_REGL(mcspi_base + SPI_MODULCTRL, SPI_MODULCTRL_MS); // Provide the clock in master mode

if (rx_fifo)    {SETBIT_REGL(mcspi_base + SPI_CH0CONF, SPI_CONF_FFER);} // Use FIFO for Receive
if (turbo_mode) {SETBIT_REGL(mcspi_base + SPI_CH0CONF, SPI_CONF_TURBO);} // Use TURBO

// Coninuous loop
while (1) {
    read_count = 0;                                                 // Keep track of the words received
    last = 0;                                                       // Flag the last transfer
    max_words = 16;                                                 // Number of words to be receive
    if (rx_fifo) {OUT_REGL(mcspi_base + SPI_XFERLEVEL, 0x100E00);} // Set the number of words to be received in the FIFO
    //debug_print("Receiving data\r\n");
    SETBIT_REGL(mcspi_base + SPI_CH0CTRL, SPI_CTRL_EN);             // Activate channel
    SETBIT_REGL(mcspi_base+SPI_IRQSTATUS, SPI_IRQSTATUS_TX0_EMPTY); // Clear TX0_EMPTY
    SETBIT_REGL(mcspi_base+SPI_IRQSTATUS, SPI_IRQSTATUS_RX0_FULL); // Clear RX0_FULL
    OUT_REGL(mcspi_base + SPI_TX0, 0);                              // Dummy TX write to start reception of data
    SETBIT_REGL(mcspi_base + SPI_CH0CTRL, SPI_CTRL_EN);             // Activate channel

    while (!last)
    {
      while(!CHKBIT_REGL(mcspi_base+SPI_IRQSTATUS, SPI_IRQSTATUS_RX0_FULL)) {} // wait for a received word
      if (rx_fifo)
      {
        for (tmp=0; tmp < max_words ; tmp++)
        {
          rx_data = PSUEDO_MCSPI_ISR(mcspi_base);
        }
      }
      else
      {
        rx_data = PSUEDO_MCSPI_ISR(mcspi_base);
      }
    }
    if (turbo_mode)
    {
      while((read_count < max_words))                                // keep going until all words
      {
        if (CHKBIT_REGL(mcspi_base+SPI_IRQSTATUS, SPI_IRQSTATUS_RX0_FULL))
        {
          rx_data = PSUEDO_MCSPI_ISR(mcspi_base);
        }
        if(CHKBIT_REGL(mcspi_base+SPI_CH0STAT, SPI_STAT_EOT)) {
          SETBIT_REGL(mcspi_base + SPI_CH0STAT, SPI_STAT_EOT);       // clear EOT
          CLRBIT_REGL(mcspi_base + SPI_CH0CTRL, SPI_CTRL_EN);        // De-activate channel
        }
      }
    }
    else
    {
      CLRBIT_REGL(mcspi_base + SPI_CH0CTRL, SPI_CTRL_EN);            // De-activate channel
      rx_data = IN_REGL(mcspi_base + SPI_RX0);
      read_count++;
    }
    //debug_print("Done read_count = %d\r\n", read_count);
}
}

//////////////////////////////////////////////////////////////////////////////////////////
// The following code would normally be called by an interrupt.
// We use a standard procedure hear since this example uses polling
//
uint32_t PSUEDO_MCSPI_ISR (uint32_t mcspi_base)
{
uint32_t rx_data;
SETBIT_REGL(mcspi_base+SPI_IRQSTATUS, SPI_IRQSTATUS_RX0_FULL); // Clear RX0_FULL

if (turbo_mode)
{
    if (read_count == (max_words - 2))
    {
      last = 1;
      CLRBIT_REGL(mcspi_base + SPI_CH0CTRL, SPI_CTRL_EN);         // De-activate channel
    }
    if (read_count < max_words)
    {
      rx_data = IN_REGL(mcspi_base + SPI_RX0);
      read_count++;
    }
}
else
{
    if (read_count == (max_words-1))
    {
      last = 1;
    } else {
      rx_data = IN_REGL(mcspi_base + SPI_RX0);
      read_count++;
    }
}
return (rx_data);
}

Let me know if you need more information.

Paul

0 PaulM over 15 years ago in reply to PaulM

TI__Mastermind 28055 points

One correction. Turbo mode does also work when the module is configures for TX/RX.

I've edited my previous post to reflect this update.

Paul

0 Bernie Thompson TI over 15 years ago in reply to PaulM

TI__Mastermind 41665 points

PaulM said:
In both TURBO and non TURBO modes the CSn line is toggled between words.

If this is the case, than why does the note above section 19.5.2.5.3 in SPRUF98d suggest that the CS will remain active?

SPRUF98d said:
The turbo mode described in Section 19.5.2.5.3, Turbo Mode, maintains SPIM_CSX in
active mode when the following conditions are met:
• A single channel is explicitly used (the SPIm.MCSPI_MODULCTRL[0] SINGLE bit is set
to 1).
• Turbo mode is enabled in the configuration of the channel. (The
SPIm.MCSPI_CHxCONF[19] TURBO bit is set to 1.)

Also, the code you have above appears to be for an AM3517 series, are the McSPI modules identical between OMAP3530 and AM3517?

Thank you for your help with this.

0 PaulM over 15 years ago in reply to Bernie Thompson TI

TI__Mastermind 28055 points

Bernie Thompson said:

If this is the case, than why does the note above section 19.5.2.5.3 in SPRUF98d suggest that the CS will remain active?

The turbo mode described in Section 19.5.2.5.3, Turbo Mode, maintains SPIM_CSX in
active mode when the following conditions are met:
• A single channel is explicitly used (the SPIm.MCSPI_MODULCTRL[0] SINGLE bit is set
to 1).
• Turbo mode is enabled in the configuration of the channel. (The
SPIm.MCSPI_CHxCONF[19] TURBO bit is set to 1.)

[/quote]

This statement is misleading.

TURBO mode itself does not maintain an active CSx. Only when the SINGLE bit is set can the CSx be maintained active. However, this must be done via software using the FORCE bit.

If you want, I can update the above code to include control of SINGLE and FORCE. It demonstrates that If SINGLE is set, then FORCE must be used and that if SINGLE is not set then FORCE has no effect.

Bernie Thompson said:

Also, the code you have above appears to be for an AM3517 series, are the McSPI modules identical between OMAP3530 and AM3517?

Correct, the code was developed on a AM3517 EVM but the McSPI modules are common so the SPI related code can be used on either platform.

Paul

0 AnBer over 14 years ago in reply to PaulM

TI__Mastermind 30150 points

Hi Paul,

PaulM said:
TURBO mode itself does not maintain an active CSx. Only when the SINGLE bit is set can the CSx be maintained active. However, this must be done via software using the FORCE bit.

A customer has got a related question but on DM37xx/AM37xx (see below in blue). I assume the same apply since the McSPI IP is similar.

I have seen that you published a nice Twiki page:
http://processors.wiki.ti.com/index.php/AM_McSpi
- Can I provide the example of this E2E post since the example is not yet published?
- Do you have a version that make use of the FORCE bit?

- I would think that for the DMA portion your McBSP DMA example should help. I guess that the majority of it would as well apply to McSPI. Correct?

Thanks and best regards,

Anthony

--------- Customer questions --------------------------------
We are trying to use the McSPI interface of the DM3730 to talk to a SPI DUART device.
We have basic FIFO driven transmit working OK out of McpSPI4 on a Beagleboard with automatic chip select generation – in this mode after each SPI word (configured as 8 bits in our setup) the chip select is disabled and re-enabled. Having the chip select disabled and re-enabled is no good for us when trying to send multi-byte commands to the DUART, the chip select needs to stay asserted for the full length of our message transfer.
To overcome this problem we have tried configuring the Force spim_csx mode (as described in section 20.5.2.5.2 of sprung4h.pdf), we now have the state where the chip select line is not being driven at all. The documentation is not very clear – what steps should be taken at the start and end of our message transfer to enable and disable the chip select line
– do we drive just the FORCE bit or is it a combination of FORCE bit and EPOL bit?
Is the Force spim_csx mode the correct way to overcome this problem?
Do you have any example code or pseudo code describing the sequence of operations?
Ideally in our “final solution” we will be driving the McSPI via DMA transfers – for each DMA transfer we want the chip select line to stay active throughout, so far we have not looked into the DMA because we couldn’t get basic FIFO operation with the FORCE bit working.
- Do you have any example code or pseudo code describing the sequence of operations for setting it up with DMA ?
On the OMAP L137 the SPI controller seems to be more advanced – it was possible to setup a DMA transfer with the tx word containing both the data and chip select control “Hold” bit - this allowed us to send a number of bytes with the chip select held active, followed by another sequence all under DMA control – is there any equivalent to this mode of operation on the DM3730?

0 PaulM over 14 years ago in reply to AnBer

TI__Mastermind 28055 points

AnBer said:

Hi Paul,

TURBO mode itself does not maintain an active CSx. Only when the SINGLE bit is set can the CSx be maintained active. However, this must be done via software using the FORCE bit.

A customer has got a related question but on DM37xx/AM37xx (see below in blue). I assume the same apply since the McSPI IP is similar.

[/quote]

The McSPI module is the same so the examples work on AM35x, AM37x, DM37x, and OMAP35x. The only thing that may need changing is the pinmuxing to suite the device/package/muxing.

AnBer said:

I have seen that you published a nice Twiki page:
http://processors.wiki.ti.com/index.php/AM_McSpi
- Can I provide the example of this E2E post since the example is not yet published?
- Do you have a version that make use of the FORCE bit?

- I would think that for the DMA portion your McBSP DMA example should help. I guess that the majority of it would as well apply to McSPI. Correct?

I have written the code in this post so you can give it to customers without issue.

In addition, I have attached some code that demonstrates the DMA and the SINGLE/FORCE mode. It's easy to switch the SINGLE mode on/off to see the effects.

AnBer said:

--------- Customer questions --------------------------------
We are trying to use the McSPI interface of the DM3730 to talk to a SPI DUART device.
We have basic FIFO driven transmit working OK out of McpSPI4 on a Beagleboard with automatic chip select generation – in this mode after each SPI word (configured as 8 bits in our setup) the chip select is disabled and re-enabled. Having the chip select disabled and re-enabled is no good for us when trying to send multi-byte commands to the DUART, the chip select needs to stay asserted for the full length of our message transfer.
To overcome this problem we have tried configuring the Force spim_csx mode (as described in section 20.5.2.5.2 of sprung4h.pdf), we now have the state where the chip select line is not being driven at all. The documentation is not very clear – what steps should be taken at the start and end of our message transfer to enable and disable the chip select line
– do we drive just the FORCE bit or is it a combination of FORCE bit and EPOL bit?
Is the Force spim_csx mode the correct way to overcome this problem?
Do you have any example code or pseudo code describing the sequence of operations?
Ideally in our “final solution” we will be driving the McSPI via DMA transfers – for each DMA transfer we want the chip select line to stay active throughout, so far we have not looked into the DMA because we couldn’t get basic FIFO operation with the FORCE bit working.
- Do you have any example code or pseudo code describing the sequence of operations for setting it up with DMA ?
On the OMAP L137 the SPI controller seems to be more advanced – it was possible to setup a DMA transfer with the tx word containing both the data and chip select control “Hold” bit - this allowed us to send a number of bytes with the chip select held active, followed by another sequence all under DMA control – is there any equivalent to this mode of operation on the DM3730?

The example attached demonstrates the manual control of the CS signal and DMA.

The devices listed earlier use a different McSPI module and there is no mechanism to control CS with an extended data bit.

Paul

MCSPI_DMA_2.zip

0 preciado88 over 12 years ago in reply to PaulM

Prodigy 30 points

Hi Paul,

I saw your example using FORCE bit to send multiple SPI words. I was wondering what would you do if you have configured the omap3 as SPI slave and want to read those words. For example, the device I'm trying to read, sends 80 bits, 5 words of 16 bits each one when the chipselect is low. When I read the RX it just appear the last 2 words, I know that the maximum length is 32 bits, but I don't know what could I do to avoid the words being overwritten.

Thanks.

Diego

0 Brad Griffis over 12 years ago in reply to preciado88

TI__Guru*** 125430 points

Diego Preciado Bar��n said:
I saw your example using FORCE bit to send multiple SPI words. I was wondering what would you do if you have configured the omap3 as SPI slave and want to read those words

If you are the SPI slave then you have no control over the assertion of the chip select, i.e. the discussion doesn't apply.

Diego Preciado Bar��n said:
For example, the device I'm trying to read, sends 80 bits, 5 words of 16 bits each one when the chipselect is low. When I read the RX it just appear the last 2 words, I know that the maximum length is 32 bits, but I don't know what could I do to avoid the words being overwritten.

There's a 64-byte FIFO integrated into the McSPI. It sounds like you're overflowing the SPI receive register. That shouldn't happen if you use the FIFO based on the transfer size you mentioned.

0 preciado88 over 12 years ago in reply to Brad Griffis

Prodigy 30 points

Hi Brad,

Brad Griffis said:

There's a 64-byte FIFO integrated into the McSPI. It sounds like you're overflowing the SPI receive register. That shouldn't happen if you use the FIFO based on the transfer size you mentioned.

As far as I know FIFO word length can only be configured between the range of 4-32 bits. I've already configured FIFO with 16-bit word length, then I have an interruption to indicate me when FIFO reaches the five words (these words come together in the same chip select when is low), but it looks like FIFO stores the last 16-bit word from five different chip selects and not the 80 bits expected.

Thanks

Diego

0 Brad Griffis over 12 years ago in reply to preciado88

TI__Guru*** 125430 points

TRM Section 19.5.4 FIFO Buffer Management said:

This buffer can be used by only one channel at once and is selected by setting SPIm.MCSPI_CHxCONF[28] FFER bit or SPIm.MCSPI_CHxCONF[27] FFEW bit to 1. If several channel are selected and several FIFO enable bit fields set to 1, the controller forces buffer not to be used, it is the responsibility of the driver to set only one FIFO enable bit field.

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OMAP3 McSPI Turbo Mode Example?