Hello all,
I tried to execute the test of DDR in the program with IPC interrupt (to wake up Core1 from Core0)
and this test worked normally before IPC. But after IPC read only test gave the error because of the code:
*(volatile uint32_t *)(IPCGR(1))=(1);
cleaned work array's content in DDR.
Assembler code:
---------------
195 DEVICE_REG32_W(IPCGR(1), 1);
$C$RL22:
00845e00: 0201222A MVK.S2 0x0244,B4
00845e04: 0201316B MVKH.S2 0x2620000,B4
00845e08: 2427 || MVK.L2 1,B0
00845e0a: 1005 STW.D2T2 B0,*B4[0]
Cleaning of the work array's content in DDR have appeared after execution of the command:
00845e0a: 1005 STW.D2T2 B0,*B4[0]
Please look complete program in the attachment.
Compiler's settings:
Debug [Active]
C6000 Compiler -> Optimization -> Optimization level -> 2
C6000 Compiler -> Advanced Optimization -> Optimize for speed -> 2
Please answer on two questions:
- why did this command clean the array's content?
- what necessary to do to avoid this cleaning?
Best regards,
Stanislaw
