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[C6678, RBL] .bootLog section

Naoki Kawada
Guru 19890 points


Hi,

My customer is now trying to boot from SPI NOR flash on C6678. It looks C6678 is trying to read the beginning of boot table parameter, but no further process happens -- RBL seems getting stuck with something erros...
To do further debugging, I would like to know the exact address of .bootLog in RBL. 

The same topic was found, but it was for C665x. How about C6678 ?

And If you have any constraints for SPI NOR Flash part in RBL point of view, please let me know.

Debug status:

1. They have already succeeded to boot the application on C6678 EVM.
2. And BOOTMODE on DEVSTAT register looks correct on their target board.
3. Their Flash is Micron N25Q512A and its contents are burned by using norwriter CCS project from MCSDK (Not default project, they modified the code slightly to fit into N25Q512A). No verification error happened when running norwriter CCS project.

Best Regards,
Naoki

  • 0
    Guru 19890 points
    It is appreciated if you could provide the exact address for both PG1.0 and PG2.0.

    Best Regards,
    Naoki
  • 0
    TI__Guru* 81335 points
    Hi,

    And If you have any constraints for SPI NOR Flash part in RBL point of view, please let me know.


    Are they working on PG1.0 or PG2.0? I hope they are facing issue in custom board.

    IBL was primarily created to provide a workaround for the PLL lockup issue (please refer to C6678 errata document, February 2011, advisory 8 for details on the PLL lockup issue). On the EVM, for ROM boot modes (EMAC,SRIO,PCIe,Hyperlink etc) and I2C boot mode with bus address 0x50, DSP will initially boot from I2C EEPROM bus address 0x51 which does the PLL reset workaround, updates the DEVSTAT for appropriate values based on the DIP switch settings (SW3 through SW6 settings) and then re enters the ROM to accomplish the desired boot mode.

    If you plan to use the latest version of the silicon(PG2.0), the PLL lock up issue has been fixed int the ROM code so you don`t need to implement the work around through a secondary I2C boot.

    It is appreciated if you could provide the exact address for both PG1.0 and PG2.0.

    I am checking with factory team and will get back to you shortly.

    Thank you.
  • 0 in reply to Raja
    Guru 19890 points
    Hello Raja,

    They are working on PG1.0. The target board is not EVM but their original board. And they are not using IBL at all.
    As for PLL lock up issue on PG1.0, I think it is not related to this issue because their boot mode is SPI. In SPI boot mode, RBL should leave PLL bypass state.

    I'm waiting for your feedback for .bootLog section. If possible, please provide the information for .fname also.

    Thank you.
    Naoki
  • 0 in reply to Naoki Kawada
    TI__Guru* 81335 points

    For C6678 the log is at 0x873200. It has the following format:

    /* The log entry format */

typedef struct bootLogEntry_s  {

   void    *fileName;     /* Pointer to a string containing the name of the file which is logging */

   UINT32   line;         /* The log line number */

   SINT32   logCode;      /* The log code */

} bootLogEntry_t;

#ifdef BOOTCONFIG_N_BOOTLOG_ENTRIES

/* The log */

typedef struct bootLog_s  {

   UINT32  idx;              /* The current Index */

   UINT32  maxIdx;           /* The max index - used for field debugging */

   UINT32  littleEndian;     /* The endianness used during compile - to decode file names */

   bootLogEntry_t entry[BOOTCONFIG_N_BOOTLOG_ENTRIES];

} bootLog_t;

extern bootLog_t     bootLog;