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AM335x DDR3 "DQS0 and DQS1"

Takahiro Ogo
Genius 5940 points
Hi,


My customer is using a AM335x with DDR3 memory (16bit-width).

If  DATA0_REG_PHY_WR_DQS_SLAVE_RATIO_0 and  DATA1_REG_PHY_WR_DQS_SLAVE_RATIO are set to same value, I understand that DQS0/DQSN0 and DQS1/DQSN1 signals become same toggle timing for write access.
Is my understanding correct?


According to my customer of the confirmation result on their board, it was different.
DQS1 toggle timing was earlier than DQS0.
      tDQSS, for DQSL (DQS0)  min 599ps--- max 655ps
      tDQSS, for DQSU (DQS1) min 363ps--- max 444ps
Of course DQS0/DQSN0 and DQS1/DQSN1 are equal-length wiring.
Why is that?


#All  DATA0_REG_XXXX and DAta1_REG_XXXX are the same value.
DDR_DATA0_IOCTRL = DDR_DATA1_IOCTRL
DATA0_REG_PHY_RD_DQS_SLAVE_RATIO_0 = DATA1_REG_PHY_RD_DQS_SLAVE_RATIO_0
DATA0_REG_PHY_WR_DQS_SLAVE_RATIO_0 = DATA1_REG_PHY_WR_DQS_SLAVE_RATIO_0
DATA0_REG_PHY_FIFO_WE_SLAVE_RATIO_0 = DATA1_REG_PHY_FIFO_WE_SLAVE_RATIO_0
DATA0_REG_PHY_WR_DATA_SLAVE_RATIO_0 = DATA1_REG_PHY_WR_DATA_SLAVE_RATIO_0

Best Regards,
Takahiro Ogo
  • 0
    TI__Guru**** 393215 points
    Hi,

    There are clearly defined guidelines for DDR3 tuning on the AM335X processor. If your customer follows them they will have no issues with their memory. We do not recommend manual adjustments to any of the EMIF registers, besides what's outlined here:
    processors.wiki.ti.com/.../AM335x_EMIF_Configuration_tips
    processors.wiki.ti.com/.../AM335x_DDR_PHY_register_configuration_for_DDR3_using_Software_Leveling
  • 0 in reply to Biser Gatchev-XID
    Genius 5940 points
    Hi,

    Yes, my customer is following the guidelines for DDR3 tuning on AM335x. (set by EMIF configure tips and Software leveling)
    The guidelines are also set to the same value in DATA0_xxx and DATA1_xxx.
    Do you have any information about my question?

    Best Regards,
    Taka
  • 0 in reply to Takahiro Ogo
    TI__Genius 9655 points

    Taka-san

    Can you share a little more information on the tDQSS measurements that you've? Are you running JEDEC compliance tests?

    Some possible reasons for the differences in the DQS0 vs. DQS1 delay could be the following:

    1) Are the layers on which the traces are routed the same? If so, do they have similar Td profile? Do they have equal VIA's? The best way to validate all of this is to run a simulation extracting the board layout

    2) Load capacitance on the memory input could have been different between DQS0 and DQS1 - I don't have the memory part/IBIS model to confirm this, but this is a likely possibility

    Regards, Siva

  • 0 in reply to sivak
    Genius 5940 points

    Hi Siva-san

    Thank you for your kind supoort. Please excuse me for the delay.


    sivak said:

    Can you share a little more information on the tDQSS measurements that you've? Are you running JEDEC compliance tests?

    They don't do JEDEC Compliance tests. But they are runining a memory timing tests with the memory manufacturer.
    As the result:
    tDQSS for DQSL(DQS0) is failed.
    tDQSS for DQSU(DQS1) is passed.
    They are wondering that there is a difference in DQS0 and DQS1 timing in spite of the fact that DATA0_xxx and DATA1_x are set the same value.


    sivak said:

    1) Are the layers on which the traces are routed the same? If so, do they have similar Td profile? Do they have equal VIA's? The best way to validate all of this is to run a simulation extracting the board layout


    Thank you for your advice. I will confirm their Layout to my customer.


    sivak said:

    2) Load capacitance on the memory input could have been different between DQS0 and DQS1 - I don't have the memory part/IBIS model to confirm this, but this is a likely possibility

    Thanks. I will check the memory side.


    #They are using a NT5CC128M16IP-DI.

    I would appreciate it very much if you could point out anything to me. 


    Best Regards,
    Taka