AM5K2E02/04 support ECC on its L1 cache ?

doner_t

Intellectual 645 points

Other Parts Discussed in Thread: AM5K2E02

Hello,

AM5K2E02/04 provide ECC on its L1 cache ? ( If I am not wrong, Cortex-A15 provide ECC on its L1 cache )

Best Regards,

Tugay

over 9 years ago

0 Raja over 9 years ago

TI__Guru* 81335 points

Hi,

Please refer and follow ARM documents for such information. As per ARM documentation(Cortex-A15 MPCore Technical Reference Manual),

1. Optional Error Correction Code (ECC) protection for L1 data cache and L2 cache, and parity protection for L1 instruction cache.

2. Refer Section "1.5 Configurable options" of Cortex-A15 MPCore Technical Reference Manual for more information.

Thank you.

0 doner_t over 9 years ago in reply to Raja

Intellectual 645 points

Thank you Raja.

So, you mean Error Correction Code(ECC) protection on the L1 cache is optional in the AM5K2E02/04 ?

Regards,
Tugay

0 Rex Chang over 9 years ago in reply to doner_t

TI__Guru 50170 points

Hi, Tugay,

ARM has it as optional, but Keystone-2 has it turned on.

Rex

0 doner_t over 9 years ago in reply to Rex Chang

Intellectual 645 points

Thank you Rex !

Let me know that Keystone-2 (especially AM5K2E02/04) provide VxWors port ? (aka OS porting)

Tugay

0 Raja over 9 years ago in reply to doner_t

TI__Guru* 81335 points

We do have VxWorks support on TI's Keystone II (K2E) devices. This is supported by windriver directly. Please check below link.

Processors

Processors forum

AM5K2E02/04 support ECC on its L1 cache ?