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urgent help regarding EDMA3 data transfer to the PaRAM set RAM Contents

Elad Fish
Prodigy 50 points


hallo every one!

i am having some trouble with my EDMA3.

i am trying to copy a block of data. when i set the destination field to a pre-define buffer it works well (the SRC data is copied to DST), but when i set DST to be an address that points to another PaRam set the  IPR reg is set properly but i dont see the data transfer. i work with the global register (not the shadow).

this is my code:

 

//----------------set PaRam A---------------------------------------------------------

//OptBit is a pointer to Param OPT field

OptBit = &(PaRam[PaRam_A].OptUnion.OptBitStruct);

//set the OPT table

OptBit->RESERVED_1 = 0;

OptBit->ITCCHEN = 0;

//If final transfer completion chaining (TCCHEN = 1 in OPT) is enabled, the chain-triggered 

//event occurs after the submission of the last transfer request of channel m is either 

//submitted or completed (depending on early or normal completion).

OptBit->TCCHEN = 0;//Transfer complete chaining is enabled

OptBit->ITCINTEN = 0;

OptBit->TCINTEN = 1;

OptBit->RESERVED_2 = 0;

OptBit->RESERVED_3 = 0;

OptBit->TCC = PaRam_B;

OptBit->TCCMODE = 0;

OptBit->FWID = 0;

OptBit->RESERVED_4 = 0;

OptBit->STATIC = 1;/*if STATIC=0 then linking will accure*/

OptBit->SYNCDIM = 0;

OptBit->DAM = 0;

OptBit->SAM = 0;

PaRam[PaRam_A].Src = (UINT32*)(&FPGA_PaRam);//in L2

PaRam[PaRam_A].Acnt = PARAM_STRUCT_SIZE_IN_BYTES;//number of bytes(elements)

PaRam[PaRam_A].Bcnt = 1;//number of ACNT, hsa to be >= 1

address =   (UINT32*)(ParamBaseAdd+((sizeof(PaRam)<<1)*(PaRam_B))+4);

PaRam[PaRam_A].Dst = (UINT32*)address;//(UINT32*)&(PaRam[PaRam_B].OptUnion.OptBitStruct);

PaRam[PaRam_A].SrcBidx = 0;

PaRam[PaRam_A].DstBidx = 0;

PaRam[PaRam_A].Link = 0xffff;

  //PaRAM-base-relative value is 0000h to 3FFFh.

PaRam[PaRam_A].BcntRld = 0;

PaRam[PaRam_A].SrcCidx = 0;

PaRam[PaRam_A].DstCidx = 0;

PaRam[PaRam_A].Ccnt = 1;

MemoryRegsMap->ESR |= (1<<PaRam_A);

 

thanks to all !!

 

  • 0
    TI__Guru* 84110 points

    I cannot tell you the exact solution because you did not identify the DSP you are using. And I cannot point you to the exact document for the answer for the same reason.

    But most likely it is the same problem I spent at least a day trying to figure out a long time ago on the first C64x+ device with EDMA3.

    In the device datasheet, in the section on System Interconnect, there will be a table that shows which internal bus Masters are connected to which bus Slave ports. For the C6455, for example, the EDMA3 PARAM (part of the EDMA3CC or TPCC in some datasheets) resides on the slave side of the CFG SCR shown in Figure 4-2 in sprs276, and the Data SCR is on the Master side of the CFG SCR in that figure. Figure 4-1 shows the EDMA3 Transfer Controllers on the Master side of the Data SCR, and shows the CFG SCR is on the Slave side. Then Table 4-1 is the SCR Connection Matrix for the Data SCR, which shows the Masters in the left hand column and the Slaves across the top.

    Looking under the CONFIGURATION SCR column, you will find there is only one TCn with a Y for a connection to the CFG SCR. This means only TC1, which does have a Y, can read from and write to the EDMA3 CC registers and PARAM. For the C6455, you would have to use a DMA channel that is configured to be in Queue 1 which is configured to map to TC1.

    You will find similar figures and tables for whichever multi-core device you are using. But that is a guess since you posted to this thread. You can find the similar figures and tables and answer for your device.

     

    If this leads you to the answer, please post the correct Transfer Controller (TCn) and DSP number to this thread and mark it with Verify Answer. If not, please post additional information or details about your question.

  • 0 in reply to RandyP
    Prodigy 50 points

    OK - you were rigth. i cant thank you enough!!!! i spent a lot of time on this issue.

    by the way i work on DSP 6457 (64+) and this the code i added:

    MemoryRegsMap->DMAQNUM[0] = 0x22222222;

    MemoryRegsMap->DMAQNUM[1] = 0x22222222;

    MemoryRegsMap->DMAQNUM[2] = 0x22222222;

    MemoryRegsMap->DMAQNUM[3] = 0x22222222;

    MemoryRegsMap->DMAQNUM[4] = 0x22222222;

    MemoryRegsMap->DMAQNUM[5] = 0x22222222;

    MemoryRegsMap->DMAQNUM[6] = 0x22222222;

    MemoryRegsMap->DMAQNUM[7] = 0x22222222;

     

    i set all channels to TC 2 instead of 0/