Hi,
The K2E DDR controller is performing HW leveling to find optimal values for the PHY.
I am assuming that part of that algorithm is finding the mid-point between the two places of were things start failing. Is there a way after the HW leveling is complete to get somehow a report of the how much margin is there between the mid-point and the start of failure?
My customer would like to know how much margin is there in the design.
Thanks,
--Gunter
Gunter,
That is beyond our support to provide code to perform this margin analysis. However, the PHY does contain registers that can be read that reflect the leveling results. There are also registers to move the leveling settings (i.e. DLL offsets). The customer can explore these registers and create code to perform this analysis. The registers are documented in the Keystone II Architecture DDR3 Memory Controller User's Guide (SPRUHN7C) at:
. There is also the Keystone II DDR3 Debug Guide (SPRAC04) available at:
that contains discussion and links to some files that may be useful.
Tom
