Hello,
We’re using the AM3354 with one Micron DDR3 x16 memory (MT41K512M16HA-125 IT:A). I have a few questions about the PCB routing rules and the write leveling:
1. We’re following the DDR3 routing guidelines from the AM3354 datasheet section 7.7.2.3. Our part placement is much closer together than the limits in Figure 7-50 (our X1 = 0 and Y = 550 mils). Our byte lanes are routed with <25 mil skew as per Table 7-67 but our nominal lengths are greater than DQLM0 and DQLM1 by 100-200 mils. DQLM0 and DQLM1 are fairly small because of the close part placement. I think that exceeding these is ok in our case because our part placement is very close. The purpose of the DQLM0 and DQLM1 restrictions seems to be to restrict the routing if the parts were placed far apart. Please confirm if exceeding them in our design is ok.
2. We have a similar issue with the CK and ADDR_CTRL nominal length (line 13 in Table 7-66). CACLM is defined as the maximum Manhattan length plus 300 mils, with the extra 300 mils to allow for routing past the DDR3 memory and back up, in the case of using two memory parts in a “fly-by” topology. We do meet the <25 mil skew requirement (line 2 in Table 7-66), but with only one part, our nominal trace lengths are 300-400 mils shorter than CACLM. Again it seems like this is because of our close part placement and only using one device. Please confirm if it’s ok for the CK and ADDR_CTRL to be shorter than the nominal length in Table 7-66.
3. In order to make routing and length matching easier, we’ve swapped pins within the byte lanes (ie. swapped DQ[7:0] within themselves and swapped DQ[15:8] within themselves). We don’t want to preclude being able to use DDR3 write leveling. JEDEC doesn’t specify on which data bit the controller expects the feedback from the memory, so the controller should be able to receive it on any data bit, allowing pin swapping. However, I’ve heard of memory controllers that require the feedback on the lowest bit of each byte (DQ0 and DQ8), which would make those bits non-swappable. Does the controller in the AM3354 require the feedback on the lowest bit, or can it be on any bit?
Thanks for your help,
Steve
