Is there an updated PCIe User's Guide for the V1 PCIe found on the AM5728?
For example, I have been looking at
KeyStone Architecture Peripheral Component Interconnect Express (PCIe) User Guide
SPRUGS6D
In that document they refer to OB_SIZE in the Outbound Translation section. However, when I look at the PCIe sample code in the PDK AM57XX package it says:
/**
* @ingroup pcielld_reg_app_structures
* @brief Specification of the Outbound Size Register
*
* On rev 0 hw, this corresponds to OB_SIZE
* On rev 1 hw, unsupported
*
* @{
*/
It seems like in Rev 1 HW it uses a multi-bit mask for the size.
/*Configure OB region for memory transfer*/ regionParams.regionDir = PCIE_ATU_REGION_DIR_OUTBOUND; regionParams.tlpType = PCIE_TLP_TYPE_MEM; regionParams.enableRegion = 1; regionParams.lowerBaseAddr = PCIE_WINDOW_MEM_BASE; regionParams.upperBaseAddr = 0; /* only 32 bits needed given data area size */ regionParams.regionWindowSize = PCIE_WINDOW_MEM_MASK; regionParams.lowerTargetAddr = obAddrLo; regionParams.upperTargetAddr = obAddrHi;
Where PCIE_WINDOW_MEM_MASK is 0x00FFFFFFU.
So, now I am confused as to how to understand how this works when the user guide and code seem to conflict.
