AM3354 DDR3 Max. Allowed DQS to CK Skew

Ned Dempsher

Other Parts Discussed in Thread: AM3354

Hi TI,

We are using the AM3354 DDR3 interface implementing the routing rules as per the datasheet.

I did not see any specifications or recommendations for maximum allowed DQS to CK routing skew. I know that this is less of an issue for DDR3 but does TI have a recommendation that we could use. We are a single memory chip implementation.

Thanks Very Much,

Ned Dempsher

L-3 Communications

over 9 years ago

0 Biser Gatchev-XID over 9 years ago

TI__Guru**** 393215 points

Hi,

There is no such requirement. Only CK to Address/control traces skew is important.

0 Ned Dempsher over 9 years ago in reply to Biser Gatchev-XID

Intellectual 260 points

Thanks Biser, We would have probably a max. of 0.3"-0.5" difference without constraining the router. Does this mean that TI can accommodate the timing ok and do you think leveling is required to do this or it that leveling isn't necessary?
Ned

0 Biser Gatchev-XID over 9 years ago in reply to Ned Dempsher

TI__Guru**** 393215 points

Yes, this should be OK. As for leveling, there is a wiki guide on tuning the DDR interface:
processors.wiki.ti.com/.../AM335x_EMIF_Configuration_tips
processors.wiki.ti.com/.../AM335x_DDR_PHY_register_configuration_for_DDR3_using_Software_Leveling

0 Ned Dempsher over 9 years ago in reply to Biser Gatchev-XID

Intellectual 260 points

Thanks Biser for Your Help,
Last question for you - wasn't quite clear. Do you think that we would have to resort to leveling to get this to work with this amount of skew or that it will meet timing without having to do this at ~250MHZ clock?
Ned

0 Biser Gatchev-XID over 9 years ago in reply to Ned Dempsher

TI__Guru**** 393215 points

Minimum allowed DDR3 clock frequency is 303MHz. For AM335X the maximum is 400MHz. The software leveling procedure described in the second wiki above is a must. It needs to be performed once per PCB design in order to establish the correct DDR PHY register values for the particular board.

0 Ned Dempsher over 9 years ago in reply to Biser Gatchev-XID

Intellectual 260 points

Got It,
Thanks Biser. After your email I just saw these specifications in the Micron Speed Bin Tables. Thanks for catching this for me.
Ned

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AM3354 DDR3 Max. Allowed DQS to CK Skew