AM335x DDR PLL tolerance

Wayne Kuo

Hi there,

My customer has a issue of tCK out of SPEC for DDR testing on customer's board.

Platform: AM335x
SDK: TI processor SDK 1.00.00.03

The tCK test result they got is 2.4961 ns, but the Low Limit of SPEC is 2.5ns.
It's 3.9 ps out of SPEC.
I think it's allowable error for the DDR test, but customer has to convince his boss and his customer this eorror is allowable tolerance.
After I discuss with customer, we think this error might cause by PLL tolerance.
However, I can't find how to calculate the DDR PLL tolerance on TRM.

Is there any formula can help me to find the DDR PLL tolerance?
Do anyone has any suggestion for this issue?
Any information would be appreciated.

Thanks and Regards,
Wayne Kuo

over 9 years ago

0 Biser Gatchev-XID over 9 years ago

TI__Guru**** 393215 points

Hi,

What is the crystal frequency they use? What is the DDR memory type - DDR2 or DDR3?

0 Wayne Kuo over 9 years ago in reply to Biser Gatchev-XID

Intellectual 870 points

Hi Biser,

DDR frequency is 400M Hz.
DDR memory type is DDR3, using Micron MT41K256M16HA-125.

Thanks and Regards,
Wayne Kuo

0 Biser Gatchev-XID over 9 years ago in reply to Wayne Kuo

TI__Guru**** 393215 points

I am asking about the OSC0 crystal frequency, not about DDR frequency.

0 Wayne Kuo over 9 years ago in reply to Biser Gatchev-XID

Intellectual 870 points

Hi Biser,

My mistake, the OSC0 frequency is 24M Hz. Thank you.

Thank you and Regards,
Wayne Kuo

0 Wayne Kuo over 9 years ago in reply to Biser Gatchev-XID

Intellectual 870 points

Hi Biser,

Is there any useful information?

Thank you and Regards,
Wayne Kuo

0 Biser Gatchev-XID over 9 years ago in reply to Wayne Kuo

TI__Guru**** 393215 points

Feedback will be posted directly here when available.

0 sivak over 9 years ago in reply to Biser Gatchev-XID

TI__Genius 9655 points

What is the DDR memory speed grade you are using? Per JEDEC spec JESD79-3E, tCK (avg) should be >=2.5ns and <=3.3ns for a DDR-800 speed grade part. This is calculated over a consecutive 200 cycle window rising edge to rising edge.

I doubt the memory part is DDR-800 speed grade since DDR-800 speed grade parts are not available. There are 2 options you have:

- Reduce the DDR clock frequency to <400MHz e.g. 395MHz

- Use the correct speed grade of the exact DDR memory when you perform the compliance tests (i.e. if the DDR memory part is 1600, use the tCK pass/fail crietria)

Regards, Siva

0 Wayne Kuo over 9 years ago in reply to sivak

Intellectual 870 points

Hi Siva,

Thanks for your reply.

You are right! We use Micron MT41K256M16HA-125 for DDR, and its speed grade is 1600.
However, AM335x use 400 MHz or 303 MHz for default DDR frequency.
We have suggested custommer to reduce the DDR frequency to < 400MHz, but they want to have a theory to support this point.

Do you have any suggestion for this?

Thank you and Regards,
Wayne Kuo

0 sivak over 9 years ago in reply to Wayne Kuo

TI__Genius 9655 points

The key thing to review is why the DDR clock output is >400MHz. So, you should review the PPM of the crystal and also check for any measurement errors.

My understanding of the JEDEC tCK (Avg) specification is validating the DDR memory capability and set the CL/CWL parameters accordingly. So, technically if you are using a higher speed grade part i.e. DDR-1600, you should be able to use a different combination of CWL/CL and still meet the tCK(avg) JEDEC specification

For eg. for CL=5/CWL=5 tCK(avg) >=2.5ns and <=3.3ns. But, with a CL=6/CWL=6 tCK(avg) >=1.875ns and <=2.5ns

Regards, Siva

0 JJD over 9 years ago in reply to sivak

TI__Guru* 86900 points

Wayne, that SDK may not have an optimal configuration for the DDR PLL, which can cause excessive jitter. Can you try to adjust the configuration of the DDR PLL to the following (for 24MHz input clock):

N = 2
M = 50
M2 = 1

This will yield a 400MHz DDR clock with the lowest jitter.

Regards,
James

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AM335x DDR PLL tolerance