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AM335X Decoupling Clarification

Ned Dempsher
Intellectual 260 points

Good Morning,

I need a clarification on decoupling as per Table 5-14 Power Supply Decoupling Capacitor Characteristics.

We have two groups of supplies:

1. 1.8V connecting together SRAM_MPU_BB and SRAM_CORE_BG. The table specifies 10.01uF for each row entry. Our design engineer has supplied only a single 10uF capacitor because both pins are tied together. The question is: Should we supply 2-10uF capacitors to provide decoupling or is only a single 10uF capacitor required to decouple both pins? (It looks like they supply separate LDOs in the part so I am concerned that 2-10uF capacitors are required and this is the way I interpret the Table.

2. Same question for the VDDSHV1-6 supplies. These are all tied together to a 3.3V supply in our designs but there is 10uF for each row entry in the Table. The question is: Is a single 10uF capacitor adequate to decouple all 6 supplies simultaneously or should we use 6-10uF capacitors, one for each. We have two different board designs. One engineer has placed 6 capacitors while the other only one so it would be great for you to clarify this for us.

Thanks TI,

Ned

  • 0
    TI__Guru**** 393215 points
    Hi,

    1. Generally 2x10uF are required, but your board may work well enough with one, depending on placement an power traces layout.
    2. Here one 10uF capacitor is not enough. I suggest you use the design with 6 capacitors.
  • 0 in reply to Biser Gatchev-XID
    Intellectual 260 points
    Thanks Biser for the Quick Response,
    Ned
  • 0 in reply to Ned Dempsher
    TI__Guru 62855 points

    The past few replies to this post seem to only mention bulk capacitors.

    I wanted to make sure you understand each AM335x power rail requires a bulk capacitor and a high frequency capacitor located near the power terminals to provide a low impedance energy source during power transients. In some cases it may acceptable to share bulk capacitors with multiple power rails, but each power rail should have a dedicated high frequency capacitor(s).

    The power rails mentioned in this post require a 10uF bulk capacitor and one or more high frequency capacitor(s). For example, the VDDSHV6 power rail requires one 10uF bulk capacitor and six 0.1uF high frequency capacitors.  The high frequency capacitors need to be distributed among all terminals of the specific power rail and shall be located very close and connected to the respective power and ground terminals with low-inductance current paths. The bulk capacitors are normally larger components that may not fit near the power terminals. They should be placed as close as possible to the group of power pins without compromising to position of high frequency capacitors.  Priority should be given to the placement of high frequency capacitors over placement of bulk capacitors.

    The capacitor values provided in the data sheet are provided as a starting point for a AM335x power distribution network (PDN) design.  The power sources, PCB design, and selected decoupling capacitors have a significant impact on PDN performance.  Modeling the PDN with actual component parameters is the best way to minimize the number of design iterations required to achieve an acceptable level of PDN performance. To prevent unexpected PDN issues, performance should be characterized using examples of the final product while operating across the entire range of operating conditions.

    Regards,
    Paul

  • 0 in reply to peaves
    Intellectual 260 points
    Thanks Very Much Paul. I was aware of the high freq. cap recommendations as well. I usually try to use analysis tools when I have time. Excel spreadsheet for capacitor analysis in early design phase followed by SIwave for post route verification AC impedance and DCIR drop. I'm very time constrained on this design though as I'm doing three boards at once but plan on follow-up with analysis. In order to have a metric I need to be able to estimate transient current (to come up with target impedance) and required outside-of-the-package bandwidth to meet the target impedance. Does TI have any recommendations on what to design to for their supplies - bandwidth and transient current? Ned
  • 0 in reply to peaves
    Intellectual 260 points
    Hi Paul,
    Don't know whether you've had a chance to look at my reply. I've pasted my question for you below as I would need this information to do a proper analysis:

    In order to have a metric I need to be able to estimate transient current (to come up with target impedance) and required outside-of-the-package bandwidth to meet the target impedance. Does TI have any recommendations on what to design to for their supplies - bandwidth and transient current? Ned

    Thanks Paul,
    Ned
  • 0 in reply to Biser Gatchev-XID
    Intellectual 260 points

    Hi Biser,

    I was wondering if you could help me in regards to this very related question to Paul from TI who responded that these datasheet guidelines are only a start and a PDN impedance versus frequency simulation of some kind incorporating high frequency ceramics is warranted. We have done this in the past using SIwave but in order to do this I would need from TI the estimated value for transient currents and the required bandwidth to meet for my PDN impedance versus frequency plots. I responded to Paul twice asking for any information he could provide (see below) but have not heard from him. Could you or other TI folks provide any recommendations on what to use?

    Thanks Very Much,

    Ned

    Thanks Very Much Paul. I was aware of the high freq. cap recommendations as well. I usually try to use analysis tools when I have time. Excel spreadsheet for capacitor analysis in early design phase followed by SIwave for post route verification AC impedance and DCIR drop. I'm very time constrained on this design though as I'm doing three boards at once but plan on follow-up with analysis. In order to have a metric I need to be able to estimate transient current (to come up with target impedance) and required outside-of-the-package bandwidth to meet the target impedance. Does TI have any recommendations on what to design to for their supplies - bandwidth and transient current? Thanks Ned