AM5728 PLL jitter

Biser-san,

Thank you for your reply.

Our customer said "Type B:17.8ns". This is not typo.

Do you think this value is strange?

Best regards,
Michi

We will need more information from customer. Which PLLs are they measuring and how are they configured?

Also which CLKOUT pin are they using?

Please define TypeA and TypeB measurements.

We need to understand how these measurements were performed to answer this question. I have described a couple of jitter measurements below as examples of what we need to understand about the measurements.

Based on value of the result, the TypeA measurement may be a period jitter. Period jitter measures the period of each cycle and the result represents the min or max clock period relative to the average clock period. The result is normal a RMS or peak-to-peak value.

The TypeB measurement result is much larger, so it might be a N-cycle jitter measurement. N-cycle jitter measures the period of N consecutive clock periods. The PLL is adjusting its output frequency to track a multiple of the reference clock. If the PLL is configured to adjust its output at a slow rate, there may be long periods of time where the PLL output frequency is high or low in frequency relative to the desired multiple of the reference clock. If you measure N-cycle jitter during one of these periods of consecutive higher or lower frequency cycles, the measurement result would be an accumulation of N-clock periods.

Regards,
Paul

Dear Pavel-san,

Thank you for your support.

I got the below information from my customer.

Type A:
DPLL_IVA was used for measurement.
CLKSEL_DPLL_IVA (0x4A00 51AC) register's setting value : 0x0000 0601
DPLL_MULT : 6
DPLL_DIV : 1
other bits are 0x0

Type B:
DPLL_VIDEO1 was used for measurement.
PLL_CONFIGURATION1(0x5800 430C) register's setting value : 0x0000 7C02
PLL_REGM : 124
PLL_REGN : 2

Also CLKOUT1 pin(F21) was used as output port.

I don't have an information how these measurements were performed.
I will ask it to customer.

I appreciate your support.

Best regards,
Michi

Dear Pavel-san,

Thank you for your support.

I checked the customer's measurement way of PLL jitter.

Customer uses the same measurement way for TypeA and TypeB.

The below is customer's measurement way.

Trigger : the rising edge of the input clk 20MHz.

Measurement point of the jitter : Customer make 20MHz clk by pll, and output it from CLKOUT pin.  Customer measures the rising edge of the first clk ( @ CLKOUT pin) from the trigger clk(20MHz input clk).

From the above information, I think this is period jitter measurement. How do you think?

I appreciate your quick reply.

Best regards,

Michi

Dear　Paul-san,

I msitook　your name. I am very sorry.

I am still waiting your reply. Please check my information from customer, and reply me.

I appreciate your reply.

Best regards,
Michi