Problems with EtherCAT and System Time PDI Controlled

For a new product, we need to synchronize the SYNC0  signal with an external 1KHz TTL signal. 

So the idea was to use an ICEv2 board and the  SYSTEM_TIME_PDI_CONTROLLED option to let  ECAT PRU adjust the System Time. 

I couldn't find specific TI documentation on how this SYSTEM_TIME_PDI_CONTROLLED option is supposed to be used so I rely on paragraph 9.3 of Beckhoff EtherCAT Slave Controller Hardware Data Sheet (Section 1), that at the end states that when the System Time register (0x0910:0x0917) is written from the PDI interface, the distributed clocks PLL is fed with the difference between the provided system time value and the content of the DC Latch0 Time Positive Edge register (0x09B0:0x09B3). 

And so we set up the application in this way:

1. Routed the TTL signal to the Latch0 input (J3 host expansion connector, pin 3)
2. Set the Latch0 positive edge in Single Event mode
3. Set AL Event Mask register to receive latch notification through the PDI interrupt
4. Execute the following pseudo-code upon latch events:

void latch_0_positive_edge_event_handler()

{

static bool is_first_event = true ;

static UInt64 reference_time = 0 ;

static UInt64 nominal_ttl_period = 1000000; // nanoseconds 

if( is_first_event )

{

reference_time = bsp_get_latch0_posedge_time() ;

is_first_event = false ;

}

else

{

reference_time += nominal_ttl_period ;

bsp_pdi_write_system_time( reference_time );

}

}

 So the first question is: does this make sense? Is this the right way to use the SYSTEM_TIME_PDI_CONTROLLED option?

Unfortunately it seems that the call to bsp_pdi_write_system_time has no effect.  Register 0x92C (System Time Difference) is always zero. We verified this even with a scope looking at the relative phase between the TTL signal and the SYCN0 output (J3 host expansion connector, pin 7); the two kept  drifting.

 Here it follows more details about the settings and some considerations about  the code:

1. We are using  SYSBIOS Industrial SDK 2.1.1.2
2. ti\sysbios_ind_sdk_2.1.1.2\sdk\starterware\board\am335x\am335x_icev2_pinmux_data.c has been modified to properly configure the latch inputs to PRU
3. The ESC settings to get the Latch0 Positive Edge time stamp (bits in square brackets) are as follows:

   Register	Value	Description
   0x140[11]	1	Enable DC Latch unit
   0x980[4]	1	Latch 0 assigned to PDI (latch event routed to PDI interrupt)
   0x9A8[0]	1	Latch 0 positive edge in Single Event mode
   0x220[1]	1	PDI interrupt on Latch event

4. Beckhoff slave stack has been modified to receive latch notification from the PDI_Isr() function
5. To verify the functionality distributed clocks on the slave have been enabled, so as to have the SYNC0  output available to a scope
6. It turned out that it is possible to program register 0x09A8 through PDI interface when 0x980[4] == 1 (the same holds for  0x09A9 when 0x980[5] == 1) but the application does not receive any latch event notification (through the PDI interrupt). To receive them,  it is necessary to program registers  0x09A8 and  0x09A9 through ECAT interface (that is from the network side). This behaviour seems not to be correct.
7. Compiling the application with the SYSTEM_TIME_PDI_CONTROLLED, write access from ECAT interface to most of the registers in the 0x900 range (the ones involved in synchronization and latching functionalities) is disabled. To properly set up the application we had to include the  SYSTEM_TIME_PDI_CONTROLLED API but leaving the write access as in the standard case.

 Please find attached the full sample application (it includes the TwinCAT project we used to test it, too) and the modified pinmux settings.

Could anyone see what we are doing wrong? Which are the right settings?

Kind regards,

Paolo