Hi,
We are migrating from OMAP3503 to AM3703 processor. I notice with omap35 processor, the registers CM_CLKEN_PLL_xxx.xxx_DPLL_FREQSEL sets the DPLL internal frequency range. The OMAP TRM mentioned at a few places that we should try to set up the N divider so that the internal frequency(fint) for all the DPLLs are around 2MHz to reduce the PLL lock time.
I notice that the CM_CLKEN_PLL_xxx.xxx_DPLL_FREQSEL field is no longer applicable and it becomes reserved field in AM37 processor. Is it means that we no longer need to worry about setting up the DPLL's internal frequency to 2MHz?
The reason I am asking this is because we are using 26MHz as the system clock with the OMAP processor. However, there is an errata (Advisory 2.1) with AM37 processor regarding USB that force us to change the system clock from 26MHz to 19.2MHz. In order for me to get the desired output clock frequencies for all the DPLLs, I would have to drop the DPLL's internal frequency from 2MHz to 0.8MHz (19.2MHz/24) for DPLL1-DPLL4.
Is it going to cause us any problem?
Thanks
