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What is the right memory choice for different segments on DSP C6748 with 128M DDR

Hello,

I have two questions about dealing with memory on DSP C6748 with 128M DDR.

My first question is about the right memory for different types of segments. First I tried to put everything on DDR with 64K L2 Cache but then my project refused to run to main. So I had to play with the entire segment and come up with the map given below. To complete this map I moved in the linker (.cmd) file specific libraries from .text and .far to different memory. I'm wandering is there any restriction on specific segments that must be in IRAM.  

The second question is about L2 Cache memory what is the balanced size of L2 Cache so on one hand will be enough but on the second hand won't to occupy all my IRAM.

TCF file:

bios.GBL.C64PLUSL2CFG = "64k";

bios.MEM.instance("IRAM").len = 0x00030000;

bios.MEM.TEXTSEG = prog.get("DDR");

bios.MEM.GBLINITSEG = prog.get("DDR");

bios.MEM.TRCDATASEG = prog.get("DDR");

bios.MEM.SYSDATASEG = prog.get("DDR");

bios.MEM.OBJSEG = prog.get("DDR");

bios.MEM.SYSINITSEG = prog.get("DDR");

bios.MEM.RTDXTEXTSEG = prog.get("DDR");

bios.MEM.SWITCHSEG = prog.get("DDR");

bios.MEM.PINITSEG = prog.get("DDR");

bios.MEM.CONSTSEG = prog.get("DDR");

bios.MEM.DATASEG = prog.get("DDR");

bios.MEM.FARSEG = prog.get("DDR");

bios.MEM.BIOSSEG = prog.get("IRAM");

bios.MEM.CIOSEG = prog.get("L3_CBA_RAM");

bios.MEM.BSSSEG = prog.get("L3_CBA_RAM");

bios.MEM.CINITSEG = prog.get("L3_CBA_RAM");

bios.MEM.STACKSIZE = 0x4000;

bios.MEM.STACKSEG = prog.get("IRAM");

Linker (.cmd) file:

 

.text_to_IRAM

 

SECTIONS

{

    .text_to_IRAM

    {

         rts6740.lib(.text)

    } > IRAM

   .far_to_IRAM

    {

        evmc6748_emac.obj (.far)

        edma3_rm_bios.lib (.far)

        pkt_tx_que.obj (.far)

        ti.pspiom.mcbsp.a674 (.far)

        TestBoard_io.obj (.far)

         rts6740.lib (.far)

         bios.a674 (.far)

         bios6748.a674 (.far)

         pwrm.a674 (.far)

         pkt_tx.obj (.far)

         drivers.a674 (.far)

         sioboth.a674 (.far)

         rtdx64xplus.lib (.far)

    } > IRAM

}

Thanks,

Pavel

  • Pavel Livshits said:

    My first question is about the right memory for different types of segments. First I tried to put everything on DDR with 64K L2 Cache but then my project refused to run to main.

    This should work!  Can you try setting L2 cache size to 0 and see if that works?  This will be very slow, but should work.  Then set cache to 64K and that should work.  If this doesn't work, can you zip up test case and attach to this forum (for the EVM board if possible) and we'll take a look?

    Pavel Livshits said:

    The second question is about L2 Cache memory what is the balanced size of L2 Cache so on one hand will be enough but on the second hand won't to occupy all my IRAM.

    There is no easy answer to this one.   I recommend making cache full size and putting everything in external memory (like you tried originally).   And then move code to L2 carefully only if the performance is not good enough.