Hi,
I'm trying to enable external interrupt with the help of CSL but no luck for now. When I put high level on pin I see that it's raising an interrupt flag in IOINTFLG1 (GPIO12) but cpu cannot go to interrupt function. Also reading a value from pin is working fine.
The code:
/* Reference the start of the interrupt vector table */
/* This symbol is defined in file vectors.asm */
extern void VECSTART(void);
/* Global Structure Declaration */
CSL_GpioObj GpioObj;
CSL_GpioObj *hGpio;
int stat = 0;
//-----------------------------------------------------------------------------
interrupt void gpioISR(void)
{
CSL_Status status;
/* Check for GPIO Interrupt Flag Register */
if( (1 == GPIO_statusBit( hGpio, CSL_GPIO_PIN12, &status )) )
{
/* Clear GPIO Interrupt Flag Register */
GPIO_clearInt( hGpio, CSL_GPIO_PIN12 );
}
stat = 1;
}
//-----------------------------------------------------------------------------
int main(void)
{
CSL_Status status;
CSL_GpioPinConfig config;
volatile Uint32 loop;
status = SYS_setEBSR(CSL_EBSR_FIELD_SP0MODE,
CSL_EBSR_SP0MODE_2);
status |= SYS_setEBSR(CSL_EBSR_FIELD_SP1MODE,
CSL_EBSR_SP1MODE_2);
/* Disable CPU interrupt */
IRQ_globalDisable();
/* Clear any pending interrupts */
IRQ_clearAll();
/* Disable all the interrupts */
IRQ_disableAll();
/* Initialize Interrupt Vector table */
IRQ_setVecs((Uint32)(&VECSTART));
/* Open GPIO module */
hGpio = GPIO_open(&GpioObj,&status);
/* Reset the GPIO module */
GPIO_reset(hGpio);
printf("Waiting...\n");
for (loop=0; loop<0x5F5E10; loop++){}
config.pinNum = CSL_GPIO_PIN12;
config.direction = CSL_GPIO_DIR_INPUT;
config.trigger = CSL_GPIO_TRIG_RISING_EDGE;
status = GPIO_configBit(hGpio,&config);
GPIO_enableInt(hGpio,CSL_GPIO_PIN12);
// Clear any pending Interrupt
IRQ_clear(GPIO_EVENT);
IRQ_plug(GPIO_EVENT,&gpioISR);
// Enabling Interrupt
IRQ_enable(GPIO_EVENT);
while(1)
{
if(stat == 1){
printf("interrupt!!111\n");
stat = 0;
}
}
return 0;
}
Vector file:
.mmregs
.include "lpva200.inc"
.C54CM_off
.CPL_off
.ARMS_off
;//-----------------------------------------------------------------------------
; predefined stack operation modes
;//-----------------------------------------------------------------------------
; USE_RETA : 2x16-bit fast return mode (RETA used)
; NO_RETA : 2x16-bit slow return mode (RETA not used)
; C54X_STK : 32-bit fast return mode
.ref _c_int00
;.ref _sarISR
.def RST
;//-----------------------------------------------------------------------------
.sect "vectors"
.align 256
.global _VECSTART
;//-----------------------------------------------------------------------------
;//-------------------------------------------------------------------------
; Other interrupt vector definitions go here
;//-------------------------------------------------------------------------
_VECSTART:
RST: .ivec reset_isr, USE_RETA ; Reset / Software Interrupt #0
NMI: .ivec nmi_isr ; Nonmaskable Interrupt
INT0: .ivec int0_isr ; External User Interrupt #0
INT1: .ivec int1_isr ; External User Interrupt #1
TINT: .ivec tim_isr ; Timer #0 / Software Interrupt #4
PROG0: .ivec i2s0_mmc0_tx_isr ; Programmable 0 Interrupt
UART: .ivec uart_isr ; IIS #1 Receive Interrupt
PROG1: .ivec i2s0_mmc0_rx_isr ; Programmable 1 Interrupt
DMA: .ivec dma_isr ; DMA Interrupt
PROG2: .ivec i2s1_mmc1_tx_isr ; Programmable 2 Interrupt
COPROCFFT: .ivec coprocfft_isr ; Coprocessor FFT Module Interrupt
PROG3: .ivec i2s1_mmc1_rx_isr ; Programmable 3 Interrupt
LCD: .ivec lcd_isr ; LCD Interrupt
SARADC: .ivec saradc_isr ; SAR ADC Interrupt
XMT2: .ivec i2s2_tx_isr ; I2S2 Tx Interrupt
RCV2: .ivec i2s2_rx_isr ; I2S2 Rx Interrupt
XMT3: .ivec i2s3_tx_isr ; I2S3 Tx Interrupt
RCV3: .ivec i2s3_rx_isr ; I2S3 Rx Interrupt
RTC: .ivec rtc_isr ; RTC interrupt
SPI: .ivec spi_isr ; SPI Receive Interrupt
USB: .ivec usb_isr ; USB Transmit Interrupt
GPIO: .ivec gpio_isr ; GPIO Interrupt
EMIF: .ivec emif_error_isr ; EMIF Error Interrupt
I2C: .ivec i2c_isr ; IIC interrupt
BERR: .ivec berr_isr ; Bus Error Interrupt
DLOG: .ivec dlog_isr ; Emulation Interrupt - DLOG
RTOS: .ivec rtos_isr ; Emulation Interrupt - RTOS
RTDXRCV: .ivec rtdxrcv_isr ; Emulation Interrupt - RTDX receive
RTDXXMT: .ivec rtdxxmt_isr ; Emulation Interrupt - RTDX transmit
EMUINT: .ivec emuint_isr ; Emulation monitor mode interrupt
SINT30: .ivec sint30_isr ; Software Interrupt #30
SINT31: .ivec sint31_isr ; Software Interrupt #31
;//-------------------------------------------------------------------------
; Reset
;//-------------------------------------------------------------------------
.text
; .def reset_isr
; .ref _c_int00
.align 2
reset_isr:
; *port(#0x1C01) = #0x0 ; Clear idles
bit (ST1, #11) = #1 ; Disable interrupts
@IVPD_L = #(RST >> 8) || mmap()
@IVPH_L = #(RST >> 8) || mmap()
bit(ST3,#7) = #0 ; Clear bus error interrupts
bit(ST3,#2) = #1 ; shut off clockout port
bit(ST1,#13) = #0 ; shut off XF port
@#IFR0_L = #0xffff || mmap() ; clear all pending interrupts
@#IFR1_L = #0xffff || mmap()
*port(#IDLE_ICR) = #(RESERVED_ICR|IPORT_IDLE|HWA_IDLE|DPORT_IDLE)
idle
;//-----------------------------------------------------------------------------
; Reset all peripherals
;//-----------------------------------------------------------------------------
*port(#0x1C04) = 0x1
nop_16
*port(#0x1C05) = 0x00FB ; Reset all peripherals
nop_16
;//-----------------------------------------------------------------------------
; Enable EMIF
;//-----------------------------------------------------------------------------
*port(IDLE_PCGCR) = #0x0
;/* Config EMIF - System Control Regsiter */
*port(#0x1C33) = #0x0
;// for SRAM in memory card (Async_CE1)
;/* Config EMIF - ASYNC Regsiters */
*port(#0x1004) = #0x0080
*port(#0x1005) = #0x00E4
;/* Configure as 16-bit data bus */
;// Async4 ==> Async_CE1 (SRAM)
*port(#0x101C) = #0x40AD
*port(#0x101D) = #0x0020
;// Async3 ==> Async_CE0(Flash)
*port(#0x1018) = #0xFFFD
*port(#0x1019) = #0x3FFF
;// do not assign Async_CE0 and Async_CE1 for NAND
*port(#0x1060) = #0x0003
;// Turn off page mode for all Chip Selects
*port(#0x1068) = #0xFCFC
*port(#0x1069) = #0xFCFC
goto _c_int00
nmi_isr: goto nmi_isr
int0_isr: goto int0_isr
int1_isr: goto int1_isr
tim_isr: goto tim_isr
i2s0_mmc0_tx_isr: goto i2s0_mmc0_tx_isr
uart_isr: goto uart_isr
i2s0_mmc0_rx_isr: goto i2s0_mmc0_rx_isr
dma_isr: goto dma_isr
i2s1_mmc1_tx_isr: goto i2s1_mmc1_tx_isr
coprocfft_isr: goto coprocfft_isr
i2s1_mmc1_rx_isr: goto i2s1_mmc1_rx_isr
lcd_isr: goto lcd_isr
saradc_isr: goto saradc_isr
i2s2_tx_isr: goto i2s2_tx_isr
i2s2_rx_isr: goto i2s2_rx_isr
i2s3_tx_isr: goto i2s3_tx_isr
i2s3_rx_isr: goto i2s3_rx_isr
rtc_isr: goto rtc_isr
spi_isr: goto spi_isr
usb_isr: goto usb_isr
gpio_isr: goto gpio_isr
emif_error_isr: goto emif_error_isr
i2c_isr: goto i2c_isr
berr_isr:
bit(ST3,#7) = #0 ; Clear bus error interrupts
goto berr_isr
dlog_isr: goto dlog_isr
rtos_isr: goto rtos_isr
rtdxrcv_isr: goto rtdxrcv_isr
rtdxxmt_isr: goto rtdxxmt_isr
emuint_isr: goto emuint_isr
sint30_isr: goto sint30_isr
sint31_isr: goto sint31_isr
;//-----------------------------------------------------------------------------
;// Name : no_isr
;//
;// Purpose : Spurious interrupt handler
;//
;// Author :
;//
;//-----------------------------------------------------------------------------
.text
no_isr: goto no_isr
dummy_isr:
return_int
.end
And a linker file:
-stack 0x1800 /* Primary stack size */
-sysstack 0x1800 /* Secondary stack size */
-heap 0x1800 /* Heap area size */
-c /* Use C linking conventions: auto-init vars at runtime */
/* SPECIFY THE SYSTEM MEMORY MAP */
MEMORY
{
PAGE 0: /* ---- Unified Program/Data Address Space ---- */
MMR (RWIX): origin = 0x000000, length = 0x0000C0 /* MMRs */
DARAM0 (RWIX): origin = 0x0000C0, length = 0x00FF40 /* 64KB - MMRs */
SARAM0 (RWIX): origin = 0x010000, length = 0x010000 /* 64KB */
SARAM1 (RWIX): origin = 0x020000, length = 0x020000 /* 128KB */
SARAM2 (RWIX): origin = 0x040000, length = 0x00FFFF /* 64KB */
PDROM (RIX): origin = 0xff8000, length = 0x008000 /* 32KB */
PAGE 2: /* -------- 64K-word I/O Address Space -------- */
IOPORT (RWI) : origin = 0x000000, length = 0x020000
}
/* SPECIFY THE SECTIONS ALLOCATION INTO MEMORY */
SECTIONS
{
vectors :> DARAM0 ALIGN = 256
.text >> SARAM1|SARAM2|SARAM0 /* Code */
/* Both stacks must be on same physical memory page */
.stack > DARAM0 /* Primary system stack */
.sysstack > DARAM0 /* Secondary system stack */
.data >> DARAM0|SARAM0|SARAM1 /* Initialized vars */
.bss >> DARAM0|SARAM0|SARAM1 /* Global & static vars */
.const >> DARAM0|SARAM0|SARAM1 /* Constant data */
.sysmem > DARAM0|SARAM0|SARAM1 /* Dynamic memory (malloc) */
.switch > SARAM2 /* Switch statement tables */
.cinit > SARAM2 /* Auto-initialization tables */
.pinit > SARAM2 /* Initialization fn tables */
.cio > SARAM2 /* C I/O buffers */
.args > SARAM2 /* Arguments to main() */
.ioport > IOPORT PAGE 2 /* Global & static ioport vars */
}
I checked all bits in registers with the help of XDS100v2 debugger (I'm running firmware from it) and they are fine.
Could you tell me please what I'm doing wrong here? Thanks.
