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Unable to load u-boot using uart boot after generating using AIS

Harish
Intellectual 350 points
Other Parts Discussed in Thread: OMAPL138, OMAP-L138

Hi,

I am using u-boot from git://arago-project.org/git/people/sekhar/u-boot-omapl1.git.

I am using omapL138 based hawkboard.

I have compiled the u-boot using da850evm_config and tested the same on the board using "go <address>" utility in  stock u-boot.

The textbase in original config.mk is 0xc1080000, by changing to 0xc7e00000 (address i choosed for testing), i downloaded into RAM using TFTP and tested by "go 0xc7e00000".

The new u-boot boots up and i am getting the prompt.

Now, I decided to flash them into NAND, so i reverted back the config.mk to original 0xc1080000 and did the clean compilation.

Using the newly built ELF uboot, i created uart2 and nand AIS binaries using AIS utility.

But, when using UART boot utility to load the generated uart ais, it reports successfully loaded and there was no error messages. When i open teraterm and did the serial port settings, there is no prompt.

I am struck at this point, unable to load/flash new uboot using ais.

Also, i am clueless about what's happening and how to debug.

Please, guide me in completing this.

 

Thanks and Regards,

HarishKumar.V

 

 

 

  • 0
    TI__Mastermind 27585 points

    Hi HarishKumar,

    Your question would be best answered in the www.hawkboard.org forums. They have much more  information about the Hawkboard flashing procedures. Thanks

    Jeff

  • 0
    TI__Guru 62975 points

    Harish,

    Are you no longer able to see a BOOTME message when you configure the board for UART boot?

    -Tommy

  • 0
    Intellectual 330 points
    Hi Harish, I had the same problem till last evening. So hopefully the solution will be the same... I was using the instructions on http://elinux.org/Hawkboard to generate the AIS image but with the latest version of AISGen (1.5) and I never managed to generate a working AIS bootable image. (My device has got the first revision of the boot rom the D800K002) Then I switched to the command line tool...! My image can now be booted successfully. I had to adapt the *-EVM.ini file to get the right memory timing. (the one that are shown on elinux.org. Regards, Christophe
  • 0 in reply to CHli
    Intellectual 350 points

    Hi,

    thanks...

    which command line tool, where to get this.. can u share the steps/readme , how to do this.

    Thanks and Regards,

    HarishKumar.V

  • 0 in reply to Harish
    Intellectual 330 points
    Hi, You can find the latest version of the tools here :

    http://processors.wiki.ti.com/index.php/Serial_Boot_and_Flash_Loading_Utility_for_OMAP-L138

    And then you should read that :

    http://processors.wiki.ti.com/index.php/GSG:_DA8x/OMAP-L1/AM1x_DVEVM_Additional_Procedures#Flashing_Boot_Images_on_Linux_Without_CCS

    As you can see it uses a .ini file to generate the AIS image, you have to download the two ini files (available on the second link) and adapt them slightly. (memory timings). One .ini is for UART and the other must be adapter from SPI to NAND.
    If it's still doesn't work I'll try to put together a step-by-step, but haven't got the time now.
    Regards,
    Christophe
  • 0 in reply to CHli
    Intellectual 350 points

    Hi,

    thanks,

    i got the link and i am reading and understanding it.

    i have downloaded the latest one, OMAP-L138_FlashAndBootUtils_2_25.tar.gz.

    Also, the ini files, i have the following files,

    OMAP-L138_EVM_spi_D800K002.ini 

    OMAP-L138_EVM_spi.ini 

    OMAP-L138_EVM_uart_D800K002.ini 

    OMAP-L138_EVM_uart.ini

    From these, i am taking reference of _D800k002.ini files.

    I am changing the following,

    uart -> memory timings (132 Mhz to 150 Mhz)

    nand -> changing BootMode from SPIMASTER to NAND and memory timings (132 Mhz -> 150 Mhz)

    is the above changes are sufficient enough, otherwise any required.

    then, need to follow the steps given in the wiki.

    Thanks and Regards,

    HarishKumar.V

  • 0 in reply to Harish
    Intellectual 350 points

    Christophe,

    I cannot able to make it work, please send the *.ini file for UART and NAND in hawkboard.

    Thanks and Regards,

    HarishKumar.V

  • 0 in reply to Harish
    Intellectual 330 points
    Hi Harish,
    As you said you have to use the 150MHz timings, but NOT the one that are in the EVM .ini file but the one mentioned on elinux.org/hawkboard (as shown on AISGen screenshots)
    I would be happy to give you my files once I tested them a little bit more. (I didn't touch any of the other settings, like PLL and maybe the CPU is not running at the right frequency, etc. so I need to make sure ALL settings are correct before making it public)
    Regards, Christophe
  • 0 in reply to CHli
    Intellectual 350 points

    Christophe,

    thanks...

    i got the uart thing working, by changing the timing ,

    [ARM_EMIF3DDR_PATCHFXN]
    DDRPHYC1R = 0x00000043
    SDCR = 0x00134632
    SDTIMR = 0x26492a09
    SDTIMR2 = 0x7d13c722
    SDRCR = 0x00000249
    CLK2XSRC = 0x00000000

    As you told, we need to check other things, i am now trying the nand one.

     

    Thanks and Regards,

    HarishKumar.V

     

     

  • 0 in reply to Harish
    Intellectual 350 points

    Christophe,

    NAND failed for me, i am unable to get this working.

    this is the my ini file,

    ; General settings that can be overwritten in the host code
    ; that calls the AISGen library.
    [General]

    ; SPIMASTER,I2CMASTER,EMIFA,NAND,EMAC,UART,PCI,HPI,USB,MMC_SD,VLYNQ,RAW
    BootMode=NAND

    ; NO_CRC,SECTION_CRC,SINGLE_CRC
    crcCheckType=NO_CRC


    ; This section allows setting the PLL0 system clock with a
    ; specified multiplier and divider as shown. The clock source
    ; can also be chosen for internal or external.
    ;           |------24|------16|-------8|-------0|
    ; PLL0CFG0: | CLKMODE| PLLM   | PREDIV | POSTDIV|
    ; PLL0CFG1: | RSVD   | PLLDIV1| PLLDIV3| PLLDIV7|
    [PLL0CONFIG]
    PLL0CFG0 = 0x00180001
    PLL0CFG1 = 0x00000205

    ; This section allows setting up the PLL1. Usually this will
    ; take place as part of the EMIF3a DDR setup. The format of
    ; the input args is as follows:
    ;           |------24|------16|-------8|-------0|
    ; PLL1CFG0: |    PLLM| POSTDIV| PLLDIV1| PLLDIV2|
    ; PLL1CFG1: |           RSVD           | PLLDIV3|
    ;[PLL1CONFIG]
    ;PLL1CFG0 = 0x00000000
    ;PLL1CFG1 = 0x00000000

    ; This section lets us configure the peripheral interface
    ; of the current booting peripheral (I2C, SPI, or UART).
    ; Use with caution. The format of the PERIPHCLKCFG field
    ; is as follows:
    ; SPI:        |------24|------16|-------8|-------0|
    ;             |           RSVD           |PRESCALE|
    ;
    ; I2C:        |------24|------16|-------8|-------0|
    ;             |  RSVD  |PRESCALE|  CLKL  |  CLKH  |
    ;
    ; UART:       |------24|------16|-------8|-------0|
    ;             | RSVD   |  OSR   |  DLH   |  DLL   |
    ;[PERIPHCLKCFG]
    ;PERIPHCLKCFG = 0x00000000


    ;********************************************************************************
    ;******************************* 132 MHz DDR settings ***************************
    ;********************************************************************************
    ; This section allows setting up the PLL1. Usually this will
    ; take place as part of the EMIF3a DDR setup. The format of
    ; the input args is as follows:
    ;           |------24|------16|-------8|-------0|
    ; PLL1CFG0: |    PLLM| POSTDIV| PLLDIV1| PLLDIV2|
    ; PLL1CFG1: |           RSVD           | PLLDIV3|
    ;[PLL1CONFIG]
    ;PLL1CFG0 = 0x15010001
    ;PLL1CFG1 = 0x00000002

    ; This section can be used to configure the PLL1 and the EMIF3a registers
    ; for starting the DDR2 interface on ARM-boot D800K002 devices.
    ;            |------24|------16|-------8|-------0|
    ; DDRPHYC1R: |             DDRPHYC1R             |
    ; SDCR:      |              SDCR                 |
    ; SDTIMR:    |              SDTIMR               |
    ; SDTIMR2:   |              SDTIMR2              |
    ; SDRCR:     |              SDRCR                |
    ; CLK2XSRC:  |             CLK2XSRC              |
    ;[ARM_EMIF3DDR_PATCHFXN]
    ;DDRPHYC1R = 0x000000C4
    ;SDCR = 0x0A034622
    ;SDTIMR = 0x184929C8
    ;SDTIMR2 = 0xB80FC700
    ;SDRCR = 0x00000406
    ;CLK2XSRC = 0x00000000

    ;********************************************************************************
    ;******************************* 150 MHz DDR settings ***************************
    ;********************************************************************************

    ; This section allows setting up the PLL1. Usually this will
    ; take place as part of the EMIF3a DDR setup. The format of
    ; the input args is as follows:
    ;           |------24|------16|-------8|-------0|
    ; PLL1CFG0: |    PLLM| POSTDIV| PLLDIV1| PLLDIV2|
    ; PLL1CFG1: |           RSVD           | PLLDIV3|
    [PLL1CONFIG]
    PLL1CFG0 = 0x18010001
    PLL1CFG1 = 0x00000002

    ; This section can be used to configure the PLL1 and the EMIF3a registers
    ; for starting the DDR2 interface on ARM-boot D800K002 devices.
    ;            |------24|------16|-------8|-------0|
    ; DDRPHYC1R: |             DDRPHYC1R             |
    ; SDCR:      |              SDCR                 |
    ; SDTIMR:    |              SDTIMR               |
    ; SDTIMR2:   |              SDTIMR2              |
    ; SDRCR:     |              SDRCR                |
    ; CLK2XSRC:  |             CLK2XSRC              |
    [ARM_EMIF3DDR_PATCHFXN]
    DDRPHYC1R = 0x00000043
    SDCR = 0x00134632
    SDTIMR = 0x26492a09
    SDTIMR2 = 0x7d13c722
    SDRCR = 0x00000249
    CLK2XSRC = 0x00000000


    [INPUTFILE]
    FILENAME=u-boot.bin
    LOADADDRESS=0xC1080000
    ENTRYPOINTADDRESS=0xC1080000

    Thanks and Regards,

    HarishKumar.V

  • 0 in reply to Harish
    Intellectual 350 points

    Christophe,

    I am using nand write.e 0xc0700000 0x20000 0x70000 in uart mode to write u-boot-nand.ais which is generated by using the configuration which pasted in earlier mail.

    Thanks and Regards,

    HarishKumar.V

  • 0 in reply to Harish
    Intellectual 330 points
    Hi Harish, Did you ever manage to boot from NAND using your own generated AIS file ? I'm back to that now and it seems I can't make it to work. I saw a configuration file somewhere on this forum that adds configuration for PINMUX to enable the UART pins but even by doing that it still doesn't work. My UART configuration works fine.
  • 0 in reply to CHli
    Intellectual 350 points

    Hi,

    Nand does not seem to work. only UART works for me.

    i saw an suggested answer from khasim sir  in hakwboard.org mailing list,

    "The latest u-boot will be using Linux kernel kind of NAND ecc layout.
    which is different from what RBL expects (the h/w ecc layout).

    we need to follow other processors by using nandecc sw (for non u-boot
    writes) and nandecc hw (for writing u-boot)"

     

    Thanks and Regards,

    HarishKumar.V

  • 0 in reply to Harish
    Intellectual 330 points
    I couldn't find the mail in question. Do you have a link ? Does this mean we have to use the UBL to Boot U-Boot from NAND ?
  • 0 in reply to CHli
    Intellectual 350 points

    Christina,

     

    any luck .... for u it worked or not ?

  • 0 in reply to Harish
    Prodigy 10 points

    hi,,..harish

    can u upload that uart_sis.bin file what actually u generated

    vizreddi@gmail.com