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C66x interrupt triggered by external host via PCIe bus

Eddie3909
Guru 10385 points

Hi

We're planning to have a C6678 connected via PCIe to another processor. Can that processor access via PCIe the "System Interrupt Status Raw/Set Registers" (RAW_STATUS_REGx) to create an interrupt of one of the C66x cores?

We'd prefer to use MSI over the PCIe bus, but we're not sure the external processor's BIOS will support that. Consequently, we're exploring alternatives.

Many thanks

Cheers2u

Eddie

  • 0
    TI__Guru* 81335 points
    Response may be delayed due to holidays in India. Thank you for your patience
  • 0
    TI__Mastermind 28085 points
    Hi,

    Please also take a look at the other threads for the MSI usage (such as the follows). Hope it helps.
    e2e.ti.com/.../166202.aspx

    Please take a look at below thread and refer the PCIe MSI example project.
    e2e.ti.com/.../825032

    Thanks,
  • 0 in reply to Ganapathi Dhandapani95
    Guru 10385 points

    Hi Ganapathi

    Those are great links for someone who wishes to have a host MSI the C6678, but in my original post I stated that we don't have that option. We are wondering if this host can access the "System Interrupt Status Raw/Set Registers" (RAW_STATUS_REGx) to create an interrupt of one of the C66x cores.

    So sorry for not being more clear, but here is our situation/question:

    a) the host cannot MSI the C6678 DSP

    b) can the host cause an internal C6678 interrupt by writing to the RAW_STATUS_REGx?

    c) can the host access RAW_STATUS_REGx via PCIe?

    Cheers
    Eddie

  • 0 in reply to Eddie3909
    TI__Mastermind 28085 points
    Hi Eddie,

    Are you planing to configure the C6678 device as RC or EP on your design?

    The memory write transactions to generate MSI interrupts in RC are actually targeted at MSI_IRQ register. The MSI interrupt is generated as a result of the one of 32 events that is triggered by a write of MSI vector value to MSI_IRQ register in RC. Before the end point devices can issue MSI interrupts, the MSI address and data registers must be configured by system software to make sure the MSI_IRQ registers could be accessed
    correctly with proper MSI vector value.
    If there is no system software supported, the user application needs to make sure EP could issue memory write transaction to MSI_IRQ register in RC with proper MSI vector value to generate MSI interrupt in RC. For more details about how MSI interrupts are expected to behave, please see the PCIe standard specifications.
    As per the PCIe specification, an EP device can generate MSI interrupts only to RC. However, the PCIESS has a provision to allow generation of MSI interrupts from an EP to another EP. To generate an interrupt to another EP, instead of doing the memory write to a register in RC memory space, an EP can target this memory write to an analogous register in another EP device that integrates a PCIESS. This memory write would be to the BAR0 memory space where all registers are located.

    Thanks,
  • 0 in reply to Ganapathi Dhandapani95
    Guru 10385 points

    Hi Ganapathi

    Thats a good idea you've presented. I'll dig into it deeper to see if that works for us.

    Cheers

    Eddie