Phase locking the output video to sync of input in encodedecode demo on evmdm365?

There is a note in sprufg8b in section "VPFE/ISP intergration" that says there is an option to drive VPBE module with the VPFE pixel clock.  Is this the method I should use or should I be looking at the VPSS events and use OSD_INT to trigger from SDRAM read or VENC_INTto trigger from VSYNC.  I am at this stage not doing any specific OSD or video encoding and am not sure if I can use these signals if I am not specifically using these modules?

Thanks, Jinh T.

Hello,

I would suggest you to source VPBE clock from PCLK fo VPFE first. Please let us know if this solves the problem.

Thanks Paul, I am busy tracing tvp5146VSYNC to VD on evmdm365 as clocks was confusing me.  Which clock do you refer to, is it PCLK of VENC clock that I must route and maybe you can tell me which registers to configure as it is quite a battle through data sheets as there is not a diagram showing what VPBE gives out exactly and what VPBE takes in although sprufg8b on page 53 mentions that pixel clock from vpfe can drive vpbe but I am still searching where to exactly set it up.

Thanks, Jinh T.

I am also running in single-shot mode as I need to capture both fields on the input and don't know if data is really going through IPIPE as it is not configured in the code but I assume it is running and in default mode as set up in dm365_def_para.c ?  Is that then where I have to change the clock source?

Thanks, Jinh T.

Hello,

For clocking, please have a quick look at page 60 of sprufg9b.pdf.

I am not sure what that source file is. Is this under Linux?

Yes Paul it is under linux.  I am busy in dm365_def_para.c to change settings in dm365_ipipe_defs and referring to p60 of sprufg9b to incorporate setting in running encodedecode demo.  After only changing clock_select from SDRAM_CLK to PIXEL_CLK it was still out of sync so I searching for other registers to change.  As I am running demo in passthrough mode and single-shot no calls are being made to change mode from default in encoder so I am changing default in driver just to evaluate the functionality.  I assume I must setup all applicable registers for configuration of VPBE clock source as per diagram on p60?

Thanks Jinh T.

By forcing VPSS_CLK_CTRL's VPSS_MUXSEL to 0x03 I have video in sync with the pixel clock now on the output - the one video signal desn't drift relative to the other one.  My next issue is that the relative offset between the frames on the output and input is different every time I restart the application.  What I actually need is for the vertical sync's to be synchronised so that I have a fixed offset between my output and input video signals as the input signal is running from a camera with external field sync of 50Hz.

Is there a way to also configure this internal in the dm365 or do I have to go around the outside and use the VS output on TVP5146 that goes to the VD input on the dm365 for ISIF to sync to external generator?  Which registers do I need to configure for this if it is a viable solution?

Thanks Jinh T.

Jinh,

I don't know of an internal way of synchronizing V-syncs.  This would typically have to be taken care of externally to DM365.  Most applications only require clock synchronization to lock in the frame-rates at the input and output.

-Iván

Thanks for the info Ivan, it confirms my suspicions that I will have to do the frame sync around the outside and am busy to set up the evmdm365 board to do so.  My first and last try on Friday was unsuccessful and I am organising a set-up again to confirm if using the PCLK internal sync only to be sufficient befre I carry on using VD as well and having to figure out exactly how it should be done.

regards, Jinh T.