AM335x ADPLLS DCO frequency is slower than 2GHz?

Takahiro Ogo

Hi,

I am trying some ADPLLS setting to reduce LCDC Clock jitters.
And then I have a question about DPLL DISP(ADPLLS) register setting.

There are the following two cases:
1)CLK24MHz, M=891, N=15, M2=9 =>148.5MHz　=> OK
CM_DIV_M2_DPLL_DISP(0x44E004A4) : 0x00000309
CM_CLKSEL_DPLL_DISP(0x44e00454) : 0x00037B0F
CM_IDLEST_DPLL_DISP(0x44E00448) : 0x1 ※Lock

2)CLK24MHz, M=900, N=15, M2=10 => NG
CM_DIV_M2_DPLL_DISP(0x44E004A4) : 0x0000030A
CM_CLKSEL_DPLL_DISP(0x44e00454) : 0x0003DE0F
CM_IDLEST_DPLL_DISP(0x44E00448) : 0x0 ※Unlock
#I have confirmed this on AM335x EVM.

Form TRM, ADPLLS can multiply up to 2-GHz maximum. So 2) should be OK. But It becomes Unlock.
Why not? ADPLLS DCO frequency is slower than 2GHz?

Best Regards,
Taka

over 9 years ago

0 Biser Gatchev-XID over 9 years ago

TI__Guru**** 393215 points

Hi,

I will ask the factory team to comment.

0 peaves over 9 years ago in reply to Biser Gatchev-XID

TI__Guru 62855 points

The CLKDCOLDO output from the display ADPLLS is calculated with the following formula which is provided in the ADPLLS section of the TRM.

CLKDCOLDO = Oscillator (DCO) output = 2 * [M / (N+1)] * CLKINP

You are setting CLKDCOLDO to 2700MHz when you use a configuration of reference clock = 24MHz with a M value of 900, and N value of 15.

So you are operating the DCO higher than the specified operating range.

Regards,
Paul

0 Takahiro Ogo over 9 years ago in reply to peaves

Genius 5940 points

Hello Paul,

Thank you for your reply. Oh, I see.

In my setting, LCD_PCLK clock source is from CLKOUT of ADPLLS(Display PLL). So I can't use the CLKDCLDO.
Even though we don't use the CLKDCLDO, CLKDCLDO must keep the max 2GHz in ADPLLS.
Is my understanding correct?

Best Regards,
Taka

0 peaves over 9 years ago in reply to Takahiro Ogo

TI__Guru 62855 points

Yes, now you understand.

Regards,
Paul

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AM335x ADPLLS DCO frequency is slower than 2GHz?