• State TI Thinks Resolved
  • Locked Locked
  • Replies 3 replies
  • Answers 1 answer
  • Subscribers 97 subscribers
  • Views 612 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

PCIe Flow Control

Christopher Peters
Genius 3380 points
Other Parts Discussed in Thread: AM5728

I am working on the AM5728 under RTOS.  I have generated a EDMA3 based PCIe sample program to communicate with an FPGA.  I can send data to the FPGA in a loop using the transfer complete interrupt from the EDMA to flow control the loop. 

This got me thinking though.  Does the EDMA3 controller really know when the PCIe has completed a transfer or just when the EDMA3 controller had finished sending the data to the PCIe peripheral?  From what I have read the PCIe has no local feedback for flow control.  No transfer complete interrupt or FIFO status.  You can get interrupts back from the EP (legacy interrupts or MSI), but I wasn't planning to use that since we will have dedicated interrupts and those don't seem to be related to interface flow anyway. 

So, my concern was can the PCIe be overwhelmed with data and if yes, then what mechanism am I missing to control it?

  • 0
    TI__Guru**** 393215 points
    I will ask the RTOS team to comment.
  • 0
    TI__Guru* 95265 points

    When you configure the EDMA, there is an OPT register EDMA_TPCC_OPT_n

    11 TCCMODE Transfer complete code mode: Indicates the point at RW 0x0
    which a transfer is considered completed. Applies to both
    chaining and interrupt.
    0x0: Normal Completion. A transfer is considered
    completed after the transfer parameters are returned to
    the CC from the TC (which was returned from the
    peripheral)
    0x1: Early Completion, A transfer is considered
    completed after the CC submits a TR to the TC. CC
    generates completion code internally.

    If you use Normal completion, that means the transfer is completed when you find IPR bit is set.

    What if you calling the EDMA transfer contiuously with faster pace that beyond the PCIE bandwidth (e.g. You use multiple EDMA transfers overlap with each other). You will get EDMA event miss and EMR/H bit will be set. If you see EMR/H is set, you know the PCIE is overwhlemed with data and you have to slow down.

    Regards, Eric

  • 0 in reply to lding
    Genius 3380 points
    Is there some underlying HW mechanism that controls this? For example, you don't tell the EDMA controller you are transferring data to DDR memory versus UART, but clearly the UART is much slower. So, then something under the hood would make the transfer complete slower for UART versus memory transfer. I'm just trying to understand how the EDMA knows the difference.