ARM L2 Cache

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Please provide the processor part number you are referring for appropriate response.

Thank you.

1. Is it configurable between SRAM and cache?

No.

2. How is L2 Cache configured?
3. Can the L2 Cache be broken up between the cores?

In Keystone 2 devices, 4MB 4MB L2 Cache Memory Shared by all Cortex A15 Processor Cores.
• L2 cache that is:
— 512KB, 1MB, 2MB, or 4MB configurable size(4MB fixed in Keystone 2)
— 16-way set-associative cache with optional ECC protection per 64-bits.
• Duplicate copy of L1 data cache tag RAMs from each processor for handling snoop requests.
• 4-way set-associative of 512-entry L2 TLB in each processor.
• Automatic hardware pre-fetcher with programmable instruction fetch and load/store data pre-fetch distances.

Please refer Cortex™-A15 MPCore™ Technical Reference Manual and keystone data manual for more information. Thank you.

My above responses stands for K2E as well. Thank you.