DM648 GigabitEthernet Failure Problem

Hi,

Hope you have gone through the guidelines to be followed while adapting NDK for custom EMAC/PHY.

Please find some links below that discuss/highlight the changes required to adapt/port NDK for custom PHY-

http://processors.wiki.ti.com/index.php/Guidelines_when_porting_NDK_to_different_PHYs

Also the discussion thread below might be helpful -

http://e2e.ti.com/support/dsp/davinci_digital_media_processors/f/99/p/5961/22173.aspx#22173

Thanks,

Prathap.

We have Marvell 88E1111 on our board, so it is not a custom EMAC/PHY.

And the most weired thing is that all the registers of PSW and MDIO are zero, including the read only registers like MDIO Version Register. And if I view the content of the register specific address, CCS reports that it is not accessible.

Could this be a power supply or clock supply problem? I have checked the power rails and REFCLKP/N, and found nothing wrong there.

Can you please check the register values using View->Memory instead of View->Registers and tell me if you see the same values?

Thanks,

Brad

Brad Griffis and BC, Thank you two very much!

I rewrite the Gel file, and the PSW and MIDO registers are not zero any more, and can be accessed by the register viewer.

However the gigabit ethernet is still not working. Our board PHY is Marvell 88E1111 on DM648 SGMII0 port. I have add "__CPSW_MDIO_DEBUG" in build option and I get the following debug message:

TCP/IP Stack 'Hello World!' Application

Using MAC Address: 3c-2d-b7-2c-40-0e

cpsw_MDIO_Init

SetPhyMode:000021E1 Auto:1, FD10:64, HD10:32, FD100:256, HD100:128, FD1000:8192 LPBK:0

cpsw_MDIO_Init

SetPhyMode:000021E1 Auto:1, FD10:64, HD10:32, FD100:256, HD100:128, FD1000:8192 LPBK:0

 EMAC should be up and running 

EMAC has been started successfully

Registeration of the EMAC Successful

Service Status: DHCPC    : Enabled  :          : 000

Service Status: DHCPC    : Enabled  : Running  : 000

Phy: 0, State: 2/FINDING, Speed: 0, Dup: 0, Tim: 1, SMode: 63, Chng: 1

Phy: 0, State: 2/FINDING, Speed: 0, Dup: 0, Tim: 1, SMode: 63, Chng: 1

cpsw_MDIO_FindingState: PhyNum: 0

Phy: 0, State: 3/FOUND, Speed: 0, Dup: 0, Tim: 0, SMode: 63, Chng: 1

 0>: 1000 7949 0141 0cc2 01e1 0000

PhyControl: 1000, Lookback=Off, Speed=10, Duplex=Half

PhyStatus: 7949, AutoNeg=NotComplete, Link=Down

PhyMyCapability: 01E1, 1000FD=Yes, 100FD=Yes, 100HD=Yes, 10FD=Yes, 10HD=Yes

PhyPartnerCapability: 0000, 1000FD=No, 100FD=No, 100HD=No, 10FD=No, 10HD=No

cpsw_MDIO_FindingState: Timed Out looking for a Phy!

cpsw_MDIO_PhYReset(0)

Enable Phy to negotiate external connection

NWAY Advertising: FullDuplex-1000 FullDuplex-100 HalfDuplex-100 FullDuplex-10 HalfDuplex-10 

Phy: 0, State: 4/NWAY_START, Speed: 0, Dup: 0, Tim: 50, SMode: 63, Chng: 1

 0>: 1000 7949 0141 0cc2 01e1 0000

PhyControl: 1000, Lookback=Off, Speed=10, Duplex=Half

PhyStatus: 7949, AutoNeg=NotComplete, Link=Down

PhyMyCapability: 01E1, 1000FD=Yes, 100FD=Yes, 100HD=Yes, 10FD=Yes, 10HD=Yes

PhyPartnerCapability: 0000, 1000FD=No, 100FD=No, 100HD=No, 10FD=No, 10HD=No

Phy: 0, State: 5/NWAY_WAIT, Speed: 0, Dup: 0, Tim: 80, SMode: 63, Chng: 1

 0>: 1000 7949 0141 0cc2 01e1 0000

PhyControl: 1000, Lookback=Off, Speed=10, Duplex=Half

PhyStatus: 7949, AutoNeg=NotComplete, Link=Down

PhyMyCapability: 01E1, 1000FD=Yes, 100FD=Yes, 100HD=Yes, 10FD=Yes, 10HD=Yes

PhyPartnerCapability: 0000, 1000FD=No, 100FD=No, 100HD=No, 10FD=No, 10HD=No

cpsw_MDIO_FindingState: Timed Out looking for a Phy!

cpsw_MDIO_FindingState: Timed Out looking for a Phy!

cpsw_MDIO_FindingState: Timed Out looking for a Phy!

Moving this thread to the BOIS forum for NDK support.

There is some update.

I found that NDK will always check two PHYs in the ethss_dm648 HAL library. As matter of fact we only have on PHY on board connected to SGMII0. So NDK keeps reporting "timed out looking for a PHY", which means the second PHY. Initially I thought it is a connection failure, and now I find that the network connection is established already.

So I need to modify the logic to coordinate with only one PHY on 3PSW inside the ethss_dm648 HAL library for customization. Is this work difficult?