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Maximum input current allowed into unpowered Keystone DSP

fdm
Expert 1070 points


Hi,

What is the maximum allowable current into LVCMOS input pin of Keystone DSP (e.g. C6657) before DVDD18 is valid?
Will it tolerate some leakage current of a voltage level translator in disabled state (in the order of 5-10uA) or, for example, weak pull-up current of unprogrammed CPLD/FPGA (~50uA)?

BR,
   Denis

  • 0
    TI__Mastermind 42545 points

    Hi Denis,

    The IO cells for LVCMOS do not have fail-safe protection. We state in the data manual that all LVCMOS input and bidirectional pins must not be driven or pulled high until DVDD18 is present. I don't have any information on a safe amount of current that can be applies to an IO cell if DVDD18 is not present.

    Regards,

    Bill

  • 0 in reply to Bill Taboada
    TI__Mastermind 46460 points

    Denis,

    Your question raises a good point.  As Bill stated, the pins are not fail safe and must not be driven when the KeyStone DSP is not powered.  It is assumed that with proper transceivers that block signals driving to the KeyStone DSP, there could be a system solution where the device is completely powered down and all signals driving to the device are high impedance.  I have never seen a system successfully designed this way but it should be possible.  Your questions identify the challenges of this problem.

    The FPGA with weak pull-up resistors definitely breaks the rule since these cannot be turned off until after the FPGA loads its configuration.  However, if the board could be properly powered up including the KeyStone DSP while meeting all of the power/clock/reset sequencing requirements and then if the FPGA outputs are then all driven to ground before the KeyStone DSP is then properly powered back down, then this should prevent the pull-ups providing leakage current to the KeyStone DSP.

    The transceiver with the 5-10uA leakage can be overcome by adding a weak pull-down resistor to each input so that the leakage goes through the resistor to ground.  This will prevent any charge from accumulating on the KeyStone DSP input pins.

    Tom

  • 0 in reply to Tom Johnson 16214
    Expert 1070 points

    Tom,

    As far as I understand, the main point of concern is a danger of latch-up. There is no declaration of latch-up performance in many of modern processor's data sheets, but usually that latch-up current is in the range of tens or even hundreds of milliamperes. For example, the declared latch-up performance for AM335x family is 45mA minimum, although almost all of its I/O pins are not fail-safe.

    What is an approximate level of current that would be treated as safe for KeyStone family?

    Do you consider the solution implemented in some reference designs (e.g. C6657 EVM)  - Spartan-3AN FPGA usage for level translation and power domains isolation (with leakage current up to 10uA per pin) - as acceptable?

    Denis

  • 0 in reply to fdm
    TI__Mastermind 46460 points

    Denis,

    Your original question was about having a board powered while the KeyStone DSP is not powered.  This could be a perpetual situation.  This is not supported in any of our KeyStone reference designs.  The KeyStone EVMs bring up all circuits at power-on and they operate continuiously until power-down.  They are all designed to follow the power sequencing rules as indicated in the KeyStone Data Manual and the datasheets for all contained devices.  (You may find cases where the power sequence in the DM was changed after the EVM was designed.)

    As Bill said, these inputs are not fail-safe.  They are not designed to withstand any voltage or current when the KeyStone DSP is not powered.  We also have explicit rules that must be followed during board power-on and board shut-down to enable full entitlement to the device reliability specs.  I proposed a complex solution to your question.  There is no simple solution to that design requirement.

    Tom

  • 0 in reply to Tom Johnson 16214
    Expert 1070 points

    Tom,

    TMDSEVM6657LS TRM v2.1 (the last one currently available) says that DSP IO supply (VCC1V8 rail) is turned on 25ms after FPGA Core/IO have been powered (VCC1V2 and VCC1V8_AUX rails). During this time FPGA outputs to DSP are locked (held at ground). But there's some inputs to FPGA from DSP that have no external pull-down resistors (for example, DSP_HOUT) and they seem floating during startup. Moreover, there's an interval of, at least, some tens of milliseconds during every EVM power-on and much more interval at initial board bring-up when FPGA is not configured yet and almost all its pins are tri-stated, applying their leakage currents (up to 10uA for Spartan-3AN) to the unpowered DSP and apparently breaking the rule about "... any voltage or current ...".
    So I think there should be some reasonable value of current that may be treated as acceptable from the practical point of view.

    Denis

  • 0 in reply to fdm
    TI__Mastermind 46460 points

    Denis,

    You have identified a weakness in the EVM design.  That does not change the requirements.  The solution would be to ramp the IO supplies for the FPGA and the DSP simultaneously.  This is the only way to guarantee full lifetime entitlement.

    Tom