Is there any example code that sets up the SPI via the PRU in C? My code doesn't work. In fact, I can't wiggle a single thing on the SPI. Is this even possible?
No SPI drivers are running on the processor.
Turning CLK on and off does nothing, I still get a 12mhz clock. Enabling and disabling does nothing here. In fact, nothing does nothing. My PinMux is set up properly for SPI1 (CS, d0, d1 and CLK). Any ideas what may be blocking things?
Code:
void Setup()
{
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perCfg->cm_per_spi1_clkctrl_bit.modulemode = ON;
// Reset SPI/Clock (Sec. 24.2.2, pp 4781)
CT_MCSPI.mcspi_sysconfig_bit.softreset = 1; // Reset SPI hardware
while (!CT_MCSPI.mcspi_sysstatus_bit.resetdone); // Wait for reset to complete
CT_MCSPI.mcspi_ch1ctrl_bit.en = 0;
// Set Master Mode (Sec 24.3.2, pp 4789)
// In Master Mode the SPI initiates a data transfer on the data lines (SPIDAT [1:0]) and
// generates clock (SPICLK) and control signals (SPIEN) to a single SPI slave device at a time.
CT_MCSPI.mcspi_modulctrl_bit.ms = 0; // Set SPI hardware to master mode
// Set Interface Mode, D0=Recv, D1=Xmit (Sec. 24.3.1.1, pp 4783)
CT_MCSPI.mcspi_ch1conf_bit.is = 1; // D1 is reception
CT_MCSPI.mcspi_ch1conf_bit.dpe0 = 0; // D0 is transmission
CT_MCSPI.mcspi_ch1conf_bit.dpe1 = 1; // Turn off D1 transmission
// Indicate we're using chip select (CS) which is located on P9_28.
CT_MCSPI.mcspi_modulctrl_bit.pin34 = 0; // Chip select used (4-pin)
// Word length is size of outgoing data (4 bits) which instructs the MCP3202 to talk.
CT_MCSPI.mcspi_ch1conf_bit.wl = 3; // SPI word is 4 bits (0-3).
// Set SPI to Transmit/Recv Mode With Both FIFO Direction Used (pp 4800)
CT_MCSPI.mcspi_ch1conf_bit.trm = 0; // Xmit/Recv mode
CT_MCSPI.mcspi_ch1conf_bit.ffer = 1; // Enable FIFO on Recv Line
CT_MCSPI.mcspi_ch1conf_bit.ffew = 1; // Enable FIFO on Xmit Line
setSPIFreq(RATE_48MHZ);
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void setSPIFreq(uint32_t speed_hz)
{
uint32_t div = 0;
int pow2;
// Don't exceed 48MHZ for the AM335x processor.
if (speed_hz > RATE_48MHZ)
speed_hz = RATE_48MHZ;
// Calculate new clock rate based on chosen frequency.
if (speed_hz < (RATE_48MHZ / MAX_DIVIDER))
{
// If 24MHZ or below, clock G is set to 0. Calc new rate based
// on ^2 divisor by first calculating the divisor itself.
pow2 = 15;
for (div = 0; div < 15; div++)
{
if (speed_hz >= (RATE_48MHZ >> div))
pow2 = div;
}
// When CLKG is 0, EXTCLK does not need to be programmed. See
// table 24-8 in AM335x TRM on page 4797.
CT_MCSPI.mcspi_ch1conf_bit.clkg = 0;
CT_MCSPI.mcspi_ch1conf_bit.clkd = pow2;
} else {
// If great than 24MHZ, clock G is set to 1 and calculated
// divisor is max rate + selected rate divided by selected rate to
// give new setting.
div = (RATE_48MHZ + speed_hz - 1) / speed_hz;
CT_MCSPI.mcspi_ch1conf_bit.clkg = 1;
CT_MCSPI.mcspi_ch1conf_bit.clkd = ((div - 1) & 0xf);
CT_MCSPI.mcspi_ch1ctrl_bit.extclk = ((div - 1) >> 4);
}
}
