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AM5K2E04: VNCTL timing for 6-bit 6-pin mode

Gunter Schmer
Genius 14212 points

Hi,

the datasheet shows the VCNTL timing for 4-pin 6-bit mode. However it is unclear what the timing is for 6-bit 6-pin mode.

[] What timing exactly after rising reset will the VCNTL[5:0] pins be driven?

[] How long will be VCNTL[5:0] be driven?

Regards,

--Gunter

  • 0
    TI__Mastermind 42545 points

    Hi Gunter,

    We don't characterize an exact time between the release of reset and when the VCNTL pins are driven. The time varies based on the configuration of the part and the frequency of the system clock provided. Internally the device will latch the 6bit VID value to the VCNTL outputs during the device initialization some time after the reset is released. That value should be driven continuously until another PORz or RESETFULLz is presented to the part. The timing for your system will be consistent. If you probe the PORz and the VCNTL interface, you can determine the delay that will be present for your design. 

    The 6bit mode was provided on the K2 components for customers that wanted a continuous representation of the VID value and didn't want to include the external logic needed to latch the value. It is not supported by the recommended TI smart reflex power supply solutions. 

    Regards,

    Bill