L1P cache enabling on C6727

John Astrium

We are getting very poor performance out of the PADK 6727 EVM kit (running slow by a factor of about 3), and we think that it may be because the L1P cache is disabled in the standard .gel file that is shipped with the kit

It "flushes" the cache, but the code in the .gel file that was shipped with the board is:

"#define L1PICR 0x20000004

/* flush cache */

*(int *)L1PICR = (*(int * L1PICR) | 0x80000000);

/* disable cache */

CSR = (CSR & ~0x000000e0) | 0x00000080;

We do not want to use DSP/BIOS configuration, as we didn't from the start, and we don't want to revamp the entire project just for this. We are struggling to understand the bit-masks required. Could anyone give us sample code that we can insert to re-enable the L1 cache.

Really glad for any help, as we are up against it, thanks

over 15 years ago

0 clam over 15 years ago

TI__Expert 8785 points

Please take a look at this document, http://focus.ti.com/lit/ug/spru733a/spru733a.pdf (in particular the CSR register on page 39). It'll explain the different fields and values in the CSR register, so you can enable/disable the cache.

- Christina

0 John Astrium over 15 years ago in reply to clam

Prodigy 120 points

Thanks, yes this works.

For future reference on the blog, the .gel files shipped with the Lyrtech C6727 PADK EVM are WRONG......

They do

CSR = (CSR & ~0x000000e0) | 0x00000080; which is actually an invalid bit configuration for the CSR register (PCC = 4...)!

instead of

CSR = (CSR & ~0x000000e0) | 0x00000040;

But even changing this doesn't seem to enable the L1P cache in a "normal" project. Something else must be disabling the cache in their "default" configuration. We needed to add into main()

extern far cregister volatile unsigned int CSR;

CSR = (CSR & ~0xE0) | 0x40; // set CSR[7:5] = 010b

That fixes it, and immediately everything runs 3 times quicker....

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L1P cache enabling on C6727