We have a prototype design that is attempting to perform a software parallel boot using a microcontroller via the NAND interface on the EMIF. Our question is this: is there any information on the sequence of NAND interface events that the VC5505 carries out? Also what format should the boot image page pointer (BIPP) be in?. The bootloader document says that only the data lines, Read/Busy and Chip Select lines need to be connected for bootloading, however we have found that after reser the VC5505 has 4 dummy writes then asks for the device ID (but only 2 bytes instead of 4?) which requires the connection of RE and WE. The device then sends the command for a sequential read from 0x00 and reads 200 memory locations and stops, presumably because the BIPP should be at 0xC4. If we supply a 3 byte BIPP of say 0x00 0x00 0x01 (page 1) the device does not go to this page but instead asks for a device ID again. Does anyone have any experience, information or ideas about what might be happening and how to resolve it?
Thanks in advance,
Ed
