AM37x EVM (UART DMA Trigger)

Hi,

What software are you using?

I am working on BSP for Nucleus RTOS.

Thanks,
Haider

Hi Haider,

1. Could you share the values of (TLR_REG[7:4] RX_FIFO_TRIG_DMA) and (FCR_REG[7:6] RX_FIFO_TRIG) which you are setting when get the SDMA request after 3 bytes?
2. Also after what number of bytes would you like to get the SDMA request?

BR
Tsvetolin Shulev

Hi there,

Following define is used to set the request level.

#define  dma_request  1

WRITE32(base_addr + AM3X_UARTTLR_OFFSET, UART_TLR_TX_FIFO_TRIG_DMA_0 | ((dma_request>>2) << 4));

WRITE32(base_addr + AM3X_UARTFCR_OFFSET, UART_FCR_FIFO_EN | UART_FCR_TX_FIFO_LSB_1 | ((dma_request & 0x3)<<6));

Following is the almost complete function that I am using. When I don't use fine granularity and only program TLR register accordingly, everything works fine.

/* configuration mode B */
WRITE32(base_addr + AM3X_UARTLCR_OFFSET, AM3X_UARTLCR_CFG_MODE_B);

/* Enable to access enhanced features */
WRITE32(base_addr + AM3X_UARTEFR_OFFSET,
READ32(base_addr + AM3X_UARTEFR_OFFSET) | AM3X_UARTEFR_ENHANCE_FEATURE);

/* configuration mode A */
WRITE32(base_addr + AM3X_UARTLCR_OFFSET, AM3X_UARTLCR_CFG_MODE_A);

/* Enable register submode TCR_TLR */
WRITE32(base_addr + AM3X_UARTMCR_OFFSET,
READ32(base_addr + AM3X_UARTMCR_OFFSET) | AM3X_UARTMCR_TCR_TLR );

WRITE32(base_addr + AM3X_UARTTCR_OFFSET,
UART_TCR_RX_FIFO_TRIG_START_24|UART_TCR_RX_FIFO_TRIG_HALT_40
);

WRITE32(base_addr + AM3X_UARTSCR_OFFSET, READ32(base_addr + AM3X_UARTSCR_OFFSET) | UART_SCR_TX_TRIG_GRANU1 | UART_SCR_RX_TRIG_GRANU1);

/* Trigger levels DMA */
WRITE32(base_addr + AM3X_UARTTLR_OFFSET, UART_TLR_TX_FIFO_TRIG_DMA_0 | ((dma_request>>2) << 4));

/* Set DMA mode to be controlled from SCR register */
WRITE32(base_addr + AM3X_UARTSCR_OFFSET, READ32(base_addr + AM3X_UARTSCR_OFFSET) | AM3X_UARTSCR_DMAMODECTL);

/* Set DMA mode 1 */
WRITE32(base_addr + AM3X_UARTSCR_OFFSET, READ32(base_addr + AM3X_UARTSCR_OFFSET) | AM3X_UARTSCR_DMAMODE1);

WRITE32(base_addr + AM3X_UARTFCR_OFFSET, UART_FCR_FIFO_EN | UART_FCR_TX_FIFO_LSB_1 | ((dma_request & 0x3)<<6));

Hi Haider,

Could you read the values of the registers to ensure that the desired values have been set properly and they have not been overwritten?

BR
Tsvetolin Shulev

Hi Tsvetolin,

Thanks for getting back.

I have read TLR register and the value is as desired.

Unfortunately, FCR is not available in read mode.

Is fine granularity feature is being used in Linux, can you kindly guide me to that.

Regards,

Haider