Need 2 GPIO lines during boot time DSP C6678

Hi Ganapathi and Raja,

Thanks for your quick response.

My Post may be confused you or gave wrong understanding.

Let me explain it here:

I understand and able to boot my SBL/IBL from I2C_EEPROM (this path is clear for me), now I have to boot my SYSBIOS image from IBL, I get the input from DIP Switch present on my custom board, where I have 3 Flashes and based on DIP Switch I have to select my flash to boot the SYSBIOS image.

Now my question since all DSP GPIO lines needed for I2C booting at what condition/time my DIP switch input to select my flash should happen or in Other words: Can i read my GPIO lines from my IBL, if yes what configs do i need to perform to enable GPIOs as Input and consider my GPIO input fed through the DIP switches and which GPIO lines are preferred for this selection i.e., I2C mode Parameter index (bits 3-8? or any other.

Regards

Mani Kumar

Hi Ganapathi and Raja,

Any information on this.

Mani Kumar,

Please clarify if your custom board design is similar to our EVM. Do you have a FPGA which is driving the DSP_BOOTMODE pins that interprets the bootswitches and drives those pins. The value from the DSP_GPIO pins latches into the DEVSTAT registers at the time of reset/power on after this you are free to use all of these pins as GPIO pins.

So to answer your questions, The safe way for you to achieve your design would be to force a GPIO check in the IBL and drive those GPIO pins using your FPGA to whatever value corresponding to Flash 0/1/2 after SOC completes its power up sequence.

However if you are not using the PCIESS in your application board, you could use the PCIESSMODE pins on the switches to drive this input. The value of PCIESS gets latched into DEVSTAT register so you can read that value from the DEVSTAT to determine which flash to use using the check in the IBL.

Regards,
Rahul

Hi Rahul,

My custom board design is based on EVM reference which houses an FPGA to drive DSP BOOTMODE pins.

My design has PCIe communication too, So, PCIE lines i can't use for this prupose.

You point about : after reset/power on, gpio lines are free to use, it means FPGA has to drive DSP BOOT MODE pins for particular time and then it can change the values on it?

So, here FPGA has to drive for a known time? or in EVM is there any option that FPGA will come to know whether RBL booted and FPGA can change the GPIO states?

Regards
Mani Kumar

Hi Rahul,

I replied to your post, but not able to see in forum links, but i expect it reached you and awaiting for your inputs.

You point about : after reset/power on, gpio lines are free to use, it means FPGA has to drive DSP BOOT MODE pins for particular time and then it can change the values on it?

Yes. After successful reset/power on, you can use those pins as GPIO pins.

So, here FPGA has to drive for a known time? or in EVM is there any option that FPGA will come to know whether RBL booted and FPGA can change the GPIO states?

The RBL uses the BOOTCOMPLETE register, which controls the BOOTCOMPLETE pin status, to indicate the completion of the RBL boot
process. The BOOTCOMPLETE pin goes high when the boot complete bits in the BOOTCOMPLETE register for all the cores are set. The RBL sets the bits for each CorePac once it completes the boot process in the CorePac and just before it exits the process. Because of legacy implementation, the BOOTCOMPLETE bit in the register corresponding to the CorePac0 is set by the hardware.

Thank you.

Hi Raja,

Thanks alot for the details provided by you, I will try them at my end.