• State Resolved
  • Locked Locked
  • Replies 6 replies
  • Answers 2 answers
  • Subscribers 100 subscribers
  • Views 860 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

AM335x ICE V2.1 Ethernet/EtherCAT Port Mux

Igor Martinovski50
Prodigy 165 points
Other Parts Discussed in Thread: TLK110

Hi,


I am using the ICE V2.1 reference design for a project that requires EtherCAT. Looking at the AM335x ICE Rev. 2.1 EVM Block Diagram, one of the ports is multiplexed with the MII1 interface. My application does not require the MII1 interface and I need to use those pins as SPI1.

Would there be any impact to EtherCAT operation if I re-mux the MII interface and remove the HW mux going to the PHY? As far as I can see, the MII interface is not pin-muxed in the code.

What is the best way to remove the MII1/PHY mux circuitry?

(http://processors.wiki.ti.com/index.php/AM335x_Industrial_Communication_Engine_EVM_Rev2_1_HW_User_Guide#Functional_Block_Diagram_of_AM335x_ICE_2.0_EVM)


 Thanks!

  • 0
    TI__Mastermind 44306 points
    Igor,
    it is not clear to me what you want to achieve. Our EtherCAT ESC for a slave implementation does require the two PRU MII ports. The additional muxing of CPSW MII on one port can be removed in customer hardware. As nearly all pins on the device are muxed you will always need to do proper pin-mux configuration.
    Generally a good tool to help with such questions is the pin-mux tool (offline and online versions available). Did you try this already?

    Regards,
  • 0
    TI__Guru**** 393215 points
    Hi,

    Ti does not recommend doing any modifications on EVM boards by customers. You can find the ICE board schematics here: processors.wiki.ti.com/.../AM335x_Boards
  • 0 in reply to Frank Walzer
    Prodigy 165 points
    Hi Frank,

    Thanks for your quick reply.

    I have confirmed that the MII1 interface is not pin-muxed in software. I am planning to use SPI1 on C18, H16, H17, J15 and H18. However these pins are currently wired to the MII1 mux. I am having a hard time figuring out exactly how the ports are multiplexed on the ICE V2.1 (not clear on what FET_nOE does, for instance.)

    Since I am not planning to use MII1 (only the two PR MII for EtherCAT) I want to confirm that I can remove the HW muxing without breaking the PRU MII interfaces.
    Thanks,
  • 0 in reply to Biser Gatchev-XID
    Prodigy 165 points
    Hi,

    I am using the ICEv2 as a reference design. The final product will not use the actual ICEv2. It will be modified to suit our needs and a new board will be developed.
  • 0 in reply to Igor Martinovski50
    TI__Mastermind 44306 points
    Igor,

    really the use of CPSW MIIs on ICEv2 is just an option. You can't use them together with PRU MII anyway. So removing that extra board muxing is ok. Make sure you use the right MDIO interface too. The FET stuff was done to isolate the TLK110 from the SYSBOOT pins of the AM335x during reset. There are sometimes conflicting PU/PD in connected pins that drive system config during reset. This is a bit tricky and depends on phy used and the final schematic.

    Regards,
  • 0 in reply to Frank Walzer
    Prodigy 165 points
    Great,

    I plan on using the same HW as the ICEv2. It sounds like I can modify the design to use the MII pins as other functions.

    Thanks.