how to idle 5510

Hi,

Could you let me know on the below.

How  McBSP is configured to operate ? is this with externally generated clocking and frame synchronization or its internal clock ?

If its external, the external interface portion of the McBSP continues to function during periods of external clock activity. The McBSP sends a request to activate the PERIPH and DMA idle domains when it needs to be serviced. If the domains were idle, they are made idle again after the McBSP has been serviced.

If McBSP is configured to operate with internally generated clocking and frame synchronization, then it will be completely stopped.

McBSP is placed into its idle mode when the PERIPH idle domain is idle (PERIS = 1 in ISTR) and the McBSP idle enable bit is set (IDLEEN = 1 in PCR).

You can check the Idle status in ISTR - PERIS should have been set.

Can you confirm on all of the above mentioned points.

Regards

Vasanth

Hi
i have 2 McBSPs working; one for configuring the codec and one for transmitting and receiving audio with the same codec; the configuration McBSP is working on the CPU clock while the data McBSP is working on the CLKS pin with sync disabled.
here is the code i'm using (there is some configuration done on the TCF file with SWI and HWI. I tried to activate IDLE mode just after entering the SWI and before copying data to make sure the CPU is idled before execution, but still, the sound is clear and the LEDs are flashing

//include//

#include "icom_5510cfg.h"
#include "dsk5510.h"
#include "dsk5510_aic23.h"
#include "dsk5510_dip.h"
#include "dsk5510_led.h"


#include <csl.h>
#include <csl_dma.h>
#include <csl_irq.h>
#include <csl_gpio.h>
#include <csl_timer.h>
#include <csl_pwr.h>

#include<std.h>
#include<hwi.h>
#include<swi.h>
#include<log.h>


//prototypes//
void initDma (void);
void initIrq (void);
void dmaHwi (void);
void initMcBSP (void);
void processBuffer (void);
void copyData (short *inbuf, short *outbuf ,int length);
void ext0Hwi (void);
void ext1Hwi (void);
int test_bit (int byte, int bit);
int set_bit (int byte, int bit, int val);
void powerDown (void);

//declaration//

#define BUFFSIZE 1024
#define PING 0
#define PONG 1

//global variables//

short gBufferRcvPingL[BUFFSIZE/2];
short gBufferRcvPingR[BUFFSIZE/2];
short gBufferRcvPongL[BUFFSIZE/2];
short gBufferRcvPongR[BUFFSIZE/2];
short gBufferXmtPingL[BUFFSIZE/2];
short gBufferXmtPingR[BUFFSIZE/2];
short gBufferXmtPongL[BUFFSIZE/2];
short gBufferXmtPongR[BUFFSIZE/2];

int pingOrPong=PING;
Uint16 eventId;
Uint16 inter0Id;
Uint16 inter1Id;
Uint16 addr;
int x=0;
int gain=-1;
int a=0;
int b=0;
int c=0;
int d=0;
int e=0;
int ioBefore=0;
int ioAfter=0;
int ionew=0;
int test1;
int test2;

int TESTR1=0;
int TESTR2=0;
int TESTR3=0;
int TESTR4=0;
int TESTR5=0;
int TESTR6=0;
int TESTR7=0;
int TESTR8=0;

DMA_Handle hDmaXmt;
DMA_Handle hDmaRcv;
DSK5510_AIC23_CodecHandle hCodec;
MCBSP_Handle C55XX_CONTROLHANDLE_hMcbsp;
MCBSP_Handle C55XX_DMA_MCBSP_hMcbsp;

DMA_Config gDmaConfigXmt = {
DMA_DMACSDP_RMK(
DMA_DMACSDP_DSTBEN_NOBURST,
DMA_DMACSDP_DSTPACK_OFF,
DMA_DMACSDP_DST_PERIPH,
DMA_DMACSDP_SRCBEN_NOBURST,
DMA_DMACSDP_SRCPACK_OFF,
DMA_DMACSDP_SRC_DARAM,
DMA_DMACSDP_DATATYPE_16BIT
), /* Source/Destination Register - DMACSDP */
DMA_DMACCR_RMK(
DMA_DMACCR_DSTAMODE_CONST,
DMA_DMACCR_SRCAMODE_DBLINDX,
DMA_DMACCR_ENDPROG_OFF,
DMA_DMACCR_REPEAT_ALWAYS,
DMA_DMACCR_AUTOINIT_ON,
DMA_DMACCR_EN_STOP,
DMA_DMACCR_PRIO_HI,
DMA_DMACCR_FS_DISABLE,
DMA_DMACCR_SYNC_XEVT2
), /* Control Register - DMACCR */
DMA_DMACICR_RMK(
DMA_DMACICR_BLOCKIE_OFF,
DMA_DMACICR_LASTIE_OFF,
DMA_DMACICR_FRAMEIE_OFF,
DMA_DMACICR_FIRSTHALFIE_OFF,
DMA_DMACICR_DROPIE_OFF,
DMA_DMACICR_TIMEOUTIE_OFF
), /* Interrupt Control Register - DMACICR */
0, /* Lower Source Address - DMACSSAL */
0, /* Upper Source Address - DMACSSAU */
0, /* Lower Destination Address - DMACDSAL */
0, /* Upper Destination Address - DMACDSAU */
2, /* Element Number - DMACEN */
BUFFSIZE/2, /* Frame Number - DMACFN */
65536-(BUFFSIZE-1), /* Frame Index - DMACFI */
BUFFSIZE-1 /* Element Index - DMACEI */
};

DMA_Config gDmaConfigRcv = {
DMA_DMACSDP_RMK(
DMA_DMACSDP_DSTBEN_NOBURST,
DMA_DMACSDP_DSTPACK_OFF,
DMA_DMACSDP_DST_DARAM,
DMA_DMACSDP_SRCBEN_NOBURST,
DMA_DMACSDP_SRCPACK_OFF,
DMA_DMACSDP_SRC_PERIPH,
DMA_DMACSDP_DATATYPE_16BIT
), /* Source/Destination Register - DMACSDP */
DMA_DMACCR_RMK(
DMA_DMACCR_DSTAMODE_DBLINDX,
DMA_DMACCR_SRCAMODE_CONST,
DMA_DMACCR_ENDPROG_OFF,
DMA_DMACCR_REPEAT_ALWAYS,
DMA_DMACCR_AUTOINIT_ON,
DMA_DMACCR_EN_STOP,
DMA_DMACCR_PRIO_HI,
DMA_DMACCR_FS_DISABLE,
DMA_DMACCR_SYNC_REVT2
), /* Control Register - DMACCR */
DMA_DMACICR_RMK(
DMA_DMACICR_BLOCKIE_ON,
DMA_DMACICR_LASTIE_OFF,
DMA_DMACICR_FRAMEIE_OFF,
DMA_DMACICR_FIRSTHALFIE_OFF,
DMA_DMACICR_DROPIE_OFF,
DMA_DMACICR_TIMEOUTIE_OFF
), /* Interrupt Control Register - DMACICR */
0, /* Lower Source Address - DMACSSAL */
0, /* Upper Source Address - DMACSSAU */
0, /* Lower Destination Address - DMACDSAL */
0, /* Upper Destination Address - DMACDSAU */
2, /* Element Number - DMACEN */
BUFFSIZE/2, /* Frame Number - DMACFN */
65536-(BUFFSIZE-1), /* Frame Index - DMACFI */
BUFFSIZE-1 /* Element Index - DMACEI */
};
DSK5510_AIC23_Config config = { \
0x0017, /* 0 DSK5510_AIC23_LEFTINVOL Left line input channel volume */
0x0017, /* 1 DSK5510_AIC23_RIGHTINVOL Right line input channel volume */
0x01f9, /* 2 DSK5510_AIC23_LEFTHPVOL Left channel headphone volume */
0x01f9, /* 3 DSK5510_AIC23_RIGHTHPVOL Right channel headphone volume */
0x0010, /* 4 DSK5510_AIC23_ANAPATH Analog audio path control */
0x0000, /* 5 DSK5510_AIC23_DIGPATH Digital audio path control */
0x0000, /* 6 DSK5510_AIC23_POWERDOWN Power down control */
0x0043, /* 7 DSK5510_AIC23_DIGIF Digital audio interface format */
0x008d, /* 8 DSK5510_AIC23_SAMPLERATE Sample rate control */
0x0001 /* 9 DSK5510_AIC23_DIGACT Digital interface activation */
};

MCBSP_Config mcbspCfg1 = {
0x1000, /* Serial Port Control Register 1 */
0x0100, /* Serial Port Control Register 2 */
0x0000, /* Receive Control Register 1 */
0x0000, /* Receive Control Register 2 */
0x0040, /* Transmit Control Register 1 */
0x0000, /* Transmit Control Register 2 */
0x0063, /* Sample Rate Generator Register 1 */
0x2013, /* Sample Rate Generator Register 2 */
0x0000, /* Multichannel Control Register 1 */
0x0000, /* Multichannel Control Register 2 */
0x1a0a, /* Pin Control Register */
0x0000, /* Receive Channel Enable Register Partition A */
0x0000, /* Receive Channel Enable Register Partition B */
0x0000, /* Receive Channel Enable Register Partition C */
0x0000, /* Receive Channel Enable Register Partition D */
0x0000, /* Receive Channel Enable Register Partition E */
0x0000, /* Receive Channel Enable Register Partition F */
0x0000, /* Receive Channel Enable Register Partition G */
0x0000, /* Receive Channel Enable Register Partition H */
0x0000, /* Transmit Channel Enable Register Partition A */
0x0000, /* Transmit Channel Enable Register Partition B */
0x0000, /* Transmit Channel Enable Register Partition C */
0x0000, /* Transmit Channel Enable Register Partition D */
0x0000, /* Transmit Channel Enable Register Partition E */
0x0000, /* Transmit Channel Enable Register Partition F */
0x0000, /* Transmit Channel Enable Register Partition G */
0x0000 /* Transmit Channel Enable Register Partition H */
};

MCBSP_Config mcbspCfg2 = {
0x0000, /* Serial Port Control Register 1 */
0x0100, /* Serial Port Control Register 2 */
0x0140, /* Receive Control Register 1 */
0x0000, /* Receive Control Register 2 */
0x0140, /* Transmit Control Register 1 */
0x0000, /* Transmit Control Register 2 */
0x0000, /* Sample Rate Generator Register 1 */
0x0000, /* Sample Rate Generator Register 2 */
0x0000, /* Multichannel Control Register 1 */
0x0000, /* Multichannel Control Register 2 */
0x0003, /* Pin Control Register */
0x0000, /* Receive Channel Enable Register Partition A */
0x0000, /* Receive Channel Enable Register Partition B */
0x0000, /* Receive Channel Enable Register Partition C */
0x0000, /* Receive Channel Enable Register Partition D */
0x0000, /* Receive Channel Enable Register Partition E */
0x0000, /* Receive Channel Enable Register Partition F */
0x0000, /* Receive Channel Enable Register Partition G */
0x0000, /* Receive Channel Enable Register Partition H */
0x0000, /* Transmit Channel Enable Register Partition A */
0x0000, /* Transmit Channel Enable Register Partition B */
0x0000, /* Transmit Channel Enable Register Partition C */
0x0000, /* Transmit Channel Enable Register Partition D */
0x0000, /* Transmit Channel Enable Register Partition E */
0x0000, /* Transmit Channel Enable Register Partition F */
0x0000, /* Transmit Channel Enable Register Partition G */
0x0000 /* Transmit Channel Enable Register Partition H */
};

//main//

void main (void){

DSK5510_init();
DSK5510_LED_init();

initDma(); //call DMA initialization function
initIrq(); //call interrupt request initialization function
initMcBSP();

hCodec = DSK5510_AIC23_openCodec(0, &config);

//MCBSP_start(C55XX_DMA_MCBSP_hMcbsp,0xf,0xDC);
DMA_RGETH(hDmaRcv,DMACSR); //read the DMA status registers to allow next interrupt
DMA_start(hDmaRcv);
DMA_start(hDmaXmt);


PWR_FSET (ICR , PERI , 1);
PWR_FSET (ICR , CPUI , 1);
PWR_FSET (ICR , CLKGENI , 1);
//PWR_FSET (ICR , EMIFI , 1);
//PWR_FSET (ICR , DMAI , 1);
MCBSP_FSET (PCR2 , IDLEEN , 1);

powerDown();

ioBefore = GPIO_RGET (IODATA);
GPIO_RSET(IODIR, 0x00);
GPIO_RSET(IODATA, 0x00);


// Now that the DMA config regs have been transferred to the working
// regs we need to reprogram the rcv dst and xmt src config regs
addr = ((Uint32)gBufferRcvPongL) << 1;
DMA_RSETH(hDmaRcv, DMACDSAL, addr & 0xffff);
DMA_RSETH(hDmaRcv, DMACDSAU, (addr >> 16) & 0xffff);

addr = ((Uint32)gBufferXmtPongL) << 1;
DMA_RSETH(hDmaXmt, DMACSSAL, addr & 0xffff);
DMA_RSETH(hDmaXmt, DMACSSAU, (addr >> 16) & 0xffff);
}

//helping functions
void ext0Hwi(void) //those 2 interrupts were never used in this testing and where never activated
{
gain=-gain;
ionew=set_bit (ioAfter,0,1);//1
ionew=1;
GPIO_RSET(IODATA, ionew);
}

void ext1Hwi(void)
{
gain=-gain;
ionew=set_bit (ioAfter,0,1);//1
ionew=1;
GPIO_RSET(IODATA, ionew);
}

void processBuffer (void){
short PingPong;
PingPong=SWI_getmbox();


ioAfter=GPIO_RGET(IODATA);
test1 = test_bit (ioAfter, 6);
test2 = test_bit (ioAfter, 5);
if (test1==1)
{
if (test2==1)
{
ionew=0;
GPIO_RSET(IODATA, ionew);
}
}

PWR_FSET (ICR , PERI , 1);
PWR_FSET (ICR , CPUI , 1);
PWR_FSET (ICR , CLKGENI , 1);
powerDown ();

DSK5510_LED_toggle(0);

if (PingPong==PING){
DSK5510_LED_toggle(1);
copyData(gBufferRcvPingL,gBufferXmtPingL,BUFFSIZE);

// Reprogram config regs for PingL
addr = ((Uint32)gBufferRcvPingL) << 1;
DMA_RSETH(hDmaRcv, DMACDSAL, addr & 0xffff);
DMA_RSETH(hDmaRcv, DMACDSAU, (addr >> 16) & 0xffff);

addr = ((Uint32)gBufferXmtPingL) << 1;
DMA_RSETH(hDmaXmt, DMACSSAL, addr & 0xffff);
DMA_RSETH(hDmaXmt, DMACSSAU, (addr >> 16) & 0xffff);

}

else{
DSK5510_LED_toggle(2);
copyData(gBufferRcvPongL,gBufferXmtPongL,BUFFSIZE);

// Reprogram config regs for PongL
addr = ((Uint32)gBufferRcvPongL) << 1;
DMA_RSETH(hDmaRcv, DMACDSAL, addr & 0xffff);
DMA_RSETH(hDmaRcv, DMACDSAU, (addr >> 16) & 0xffff);

addr = ((Uint32)gBufferXmtPongL) << 1;
DMA_RSETH(hDmaXmt, DMACSSAL, addr & 0xffff);
DMA_RSETH(hDmaXmt, DMACSSAU, (addr >> 16) & 0xffff);

}

}

void initDma (void){
hDmaXmt=DMA_open(DMA_CHA_ANY,DMA_OPEN_RESET);
hDmaRcv=DMA_open(DMA_CHA_ANY,DMA_OPEN_RESET);

gDmaConfigXmt.dmacssal=(DMA_AdrPtr)(((Uint32)(&gBufferXmtPingL)<<1)&0x00FFFF);
gDmaConfigXmt.dmacssau=(Uint16)((((Uint32)(&gBufferXmtPingL)<<1)&0xFF000)>>16);
gDmaConfigXmt.dmacdsal=(DMA_AdrPtr)(((Uint32)(&_MCBSP_DXR12)<<1)&0x00FFFF);
gDmaConfigXmt.dmacdsau=(Uint16)((((Uint32)(&_MCBSP_DXR12)<<1)&0x00FFFF)>>16);

gDmaConfigRcv.dmacssal=(DMA_AdrPtr)(((Uint32)(&_MCBSP_DRR12)<<1)&0x00FFFF);
gDmaConfigRcv.dmacssau=(Uint16)((((Uint32)(&_MCBSP_DRR12)<<1)&0xFF000)>>16);
gDmaConfigRcv.dmacdsal=(DMA_AdrPtr)(((Uint32)(&gBufferRcvPingL)<<1)&0x00FFFF);
gDmaConfigRcv.dmacdsau=(Uint16)((((Uint32)(&gBufferRcvPingL)<<1)&0x00FFFF)>>16);

DMA_config(hDmaXmt, &gDmaConfigXmt);
DMA_config(hDmaRcv, &gDmaConfigRcv);
}
void initIrq (void){
eventId = DMA_getEventId(hDmaRcv); //get event Id from DMA interrupt
inter0Id = IRQ_EVT_INT0;
inter1Id = IRQ_EVT_INT1;

IRQ_clear(eventId);
IRQ_clear(inter0Id);
IRQ_clear(inter1Id);

IRQ_enable(eventId);
IRQ_enable(inter0Id);
IRQ_enable(inter1Id);

//IRQ_plug(eventId, &dmaHwi);
HWI_dispatchPlug(eventId,(Fxn)dmaHwi, NULL);
HWI_dispatchPlug(inter0Id,(Fxn)ext0Hwi, NULL);
HWI_dispatchPlug(inter1Id,(Fxn)ext1Hwi, NULL);

IRQ_globalEnable();
}


void dmaHwi(void)
{

DMA_RGETH(hDmaRcv, DMACSR);
if(pingOrPong==PING){
SWI_or(&processBufferSwi,PING);
pingOrPong=PONG;
}
else{
SWI_or(&processBufferSwi,PONG);
pingOrPong=PING;
}
}
void initMcBSP (void){
C55XX_CONTROLHANDLE_hMcbsp = MCBSP_open(MCBSP_PORT1, MCBSP_OPEN_RESET);
C55XX_DMA_MCBSP_hMcbsp = MCBSP_open(MCBSP_PORT2, MCBSP_OPEN_RESET);
MCBSP_config(C55XX_CONTROLHANDLE_hMcbsp, &mcbspCfg1);
MCBSP_config(C55XX_DMA_MCBSP_hMcbsp, &mcbspCfg2);
}

void copyData(short *inbuf, short *outbuf ,int length )
{
int i = 0;
for (i = 0; i < length; i++)
{
outbuf[i] = inbuf[i] << gain;
}
}

int test_bit (int byte, int bit)
{
a = 2<<(bit-1);
b= byte & a;
c = b >> bit;
if (c==0)
{
return 0;
}
else
{
return 1;
}
}

int set_bit (int byte,int bit,int val)
{
if (val==0)
{
d = 2<<(bit-1);
e = d^0xffff;
byte = byte & e;
}
if (val==1)
{
d = 2<<(bit-1);
byte = byte | d;
}
return byte;
}

void powerDown (void)
{
PWR_powerDown(PWR_WAKEUP_MI);
DSK5510_LED_toggle(3);
}

any comments?
best regards
Aziz

HI,

 Were you able to check the Idle status in ISTR - What is the value you read ? is PERIS bit set ? This might not have been set based on your explanation, but would like to reconfirm.

Regards

 Vasanth

Hi
earlier i was doing some testings, and the PERIS bat was set, but everi time i checked the CPU bit was cleared in ISTR.

now when i checked (the only thing changed here is that i also set the clock bit.) all the ISTR register is clear. any explanation? any thoughts?
best regards
aziz