TMS320C6748 HPI Boot

369114 said:

I’m going to use the HPI boot mode for the TMS320C6748 so I’m referencing “SPRAAT2B – Using the TMS320C6748/C6746/C6742 Bootloader Application Report” and "SPRUFM7D – TMS320C674x/OMAP-L1x Processor Host Port Interface (HPI) User's Guide" and I am not able to locate some information.

 

Specifically, where do I find information with regards to what registers are programmed with what values during HPI boot mode and do they remain that way after HPI boot?

 

For example, TI documentation indicates that the default after reset value of HPIRST in HPIC is 1 indicating that the HPI is held in reset.  As part of the HPI boot, I would imagine that some entity would have to clear this bit to release the HPI from reset in order to boot via the HPI and then perhaps it sets it back to 1 after HPI boot or leave it released form reset - unless there is something else going on under the hood.

 

Another example, TI documentation also indicates that default after reset value of HPIENA in CFGCHIP1 is 0 indicating that the HPI is disabled.  Again as part of the HPI boot, one would think that this bit has to be set to 1 to enable the HPI and does is stay set after HPI boot?  In the event that the Host has to participate in setting this bit, would the Host have to write to the KICK registers to again access to the CFGCHIP1 register?

 

Additionally, what address length is used during HPI boot – 0 indicating the Host address is a word address or 1 indicating the Host address is a byte address?

 

Let me know if there is anything with regards to the HPI boot and HPI initialization that I have to pay attention to that I did not mentioned here.

Some source that might answer your questions (and backs up Tim's answers):

In the UHPI open function:

  DEVICE_LPSCTransition(PSCNUM1, LPSC_UHPI0, PD0, PSC_ENABLE);

  // Set UHPI to byte-address mode in CFGCHIP1 of BOOTCFG
  SYSTEM->CFGCHIP[1] &= ~(DEVICE_CFGCHIP1_HPIBYTEAD_MASK);
  SYSTEM->CFGCHIP[1] |= (0x1 << DEVICE_CFGCHIP1_HPIBYTEAD_SHIFT);

  // Enable UHPI in CFGCHIP1 of BOOTCFG
  SYSTEM->CFGCHIP[1] &= ~(DEVICE_CFGCHIP1_HPIENA_MASK);
  SYSTEM->CFGCHIP[1] |= (0x1 << DEVICE_CFGCHIP1_HPIENA_SHIFT);

  DEVICE_pinmuxControl(13,0xFFFFFFFF,0x22222222); // UHPI_HRnW, UHPI_HHWIL, UHPI_HCNTL1, UHPI_HCNTL0, nUHPI_HINT, nUHPI_HRDY, nUHPI_HDS2, nUHPI_HAS
  DEVICE_pinmuxControl(14,0xFFFFFFFF,0x22222222); // UHPI_HD[15..10], nUHPI_HDS1, nUHPI_HCS
  DEVICE_pinmuxControl(15,0xFFFFFFFF,0x22222222); // UHPI_HD[9..2]
  DEVICE_pinmuxControl(16,0x000000FF,0x00000022); // UHPI_HD[1..0]

  // Take UHPI out of reset
  UHPI->HPIC &= ~(DEVICE_HPIC_HPIRST_MASK);
  UHPI->HPIC |=  (0x0 << DEVICE_HPIC_HPIRST_SHIFT);

369114 said:

Specifically, where do I find information with regards to what registers are programmed with what values during HPI boot mode and do they remain that way after HPI boot?

To address this, please do not rely on the configuration you see above to remain in place after boot is complete.  For boot over any peripheral interface, you should always initialize a peripheral you plan to use in your application from within your application, using the specific settings you require.  We will not guarantee that the ROM will always exit the boot loader process with a peripheral in any given state (i.e., the exit state of a peripheral could change in any future version of the chip/ROM).

Regards, Daniel