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TMS320C6748 DDR/mDDR

Other Parts Discussed in Thread: TMS320C6748

I’m questioning the accuracy of the information contained in Table 3-9. DDR2 Controller (DDR2) Terminal Functions contained in the SPRS590A – TMS320C6748Fixed/Floating Point DSP Data Sheet.

 

The table in the data sheet indicates that the active low signals DDR_WE, DDR_RAS, DDR_CAS, and DDR_CS are all internally pulled down.  Does the TMS320C6748 device really connect these active low signals to internal pull down resistors?

 

Also there is an associated footnote (Table 3-9; footnote 2) with regards to the pullup/pulldown resistor configuration.

 

(2) IPD = Internal Pulldown resistor; IPU = Internal Pullup resistor; CP[n] = configurable pull-up/pull-down (where n is the pin group) using

the PUPDENA and PUPDSEL registers in the System Module.

 

The footnote mentions that these are configurable but the table does not identify the specific pin group associated with the DDR2/mDDR pins.

What guidance can TI provide for us to follow with regards to these active low signals DDR_WE, DDR_RAS, DDR_CAS, and DDR_CS and the internal pullup/pulldown resistor pin configuration?

  • The footnotes at the bottom of page 31 are included for every table in this section, as long as there are any signals for which any of the footnotes are applicable. In this case, there are only IPDs, so the comments about IPU and CP[n] do not apply. If you look at the next table, there are several different CP's listed.

    Sorry for the confusion that the footnote caused, but these pins do not have Configurable Pulls.

  • Randy, 

    Thanks for the response.  I think we are still missing something. 

    The table in the data sheet indicates that the active low signals DDR_WE, DDR_RAS, DDR_CAS, and DDR_CS are all internally pulled down.  Does the TMS320C6748 device really connect these active low signals to internal pull down resistors?

    It doesn't make sense to us that these active low signals are actually pulled down.  Thinking that the hardware designers would have to place an external pull-up resistor on these active low signals and ultimately resulting in some small constant current draw when these signals are inactive high.

    Any additional insight is appreciated. 

     

  • Brad,

    Yes, the buffers do have internal pull downs.  I think the pull downs were chosen to simplify pin handling when the DDR interface is not used.  When a DDR memory is hooked up to the interface, external pulls are not required (and should not be used).  The signals will be actively driven by C6748 / DDR. 

    -Tommy

  • I need to know the min & max values for the TMS320C6748 internal pullups and pulldonwns after boot as well as the "week pullups" at boot.

  • Please find the Ii spec (Input current) in the datasheet, section 5.3 page 67. This is the available specification for the IPU/IPDs.

  • If I am reading the datasheet correctly, I can expect a max of 270 uA if I try to pullup an input when it is pulled down. That is the equivalent of a 12K internal resistor that I have to overcome (for a 3.3V input).  Is that true?  The footnote says it applies only to IPD, but I don't see data on the weak pulldowns during reset that I need to overcome so I assume they are the same which will required a very strong pullup to keep the signal high during the boot process until the software can turn off the internal resistor.  But then that strong resistor is there after boot as well which will increase my power dissipation.

  • Yes, the IPD mentioned in the datasheet are the same structures activated during reset.  External pulls are only required for signals that must remain at a static level during reset.  Under typical use conditions DDR does not require any external pulls.

    -Tommy