ARM DSP communication in OMAPL137

pramodbk

Other Parts Discussed in Thread: OMAP-L137

Hi,

I am trying to come up with a simple program which does ARM - DSP communication in OMAPL137. From the OMAPL137 data sheet it is mentioned that the SYSCFG module has a set of registers to facilitate interprocessor communication. Also ARM interrupts the DSP when it has to send data to the DSP using shared memory.

I have the following questions on how to implement the interprocess communication.

1.) Which are the registers in SYSCFG module which facilitates interprocessor communication

2.) How ARM will interrupt the DSP. Which are the registers for doing this.

3.) Which is the interrupt in DSP in the above case. Is it event number 11, EMU-RTDXRX

4.) Similarly I would like to know how to send the data from DSP to ARM. What all registers I have to set in the DSP to interrupt the ARM. And which is the interrupt number in ARM in this case.

Regards,

Pramod

over 15 years ago

0 Mariana over 15 years ago

TI__Mastermind 24340 points

Hi Pramod,

Usually the DSP to ARM communication is done by a software layer between the ARM OS (Linux) and the DSP OS (DSP/BIOS). I'm assuming that you saw:

http://processors.wiki.ti.com/index.php/Getting_Started_Guide_for_OMAP-L137

If you want to use Linux and the DSP as an accelerator for algorithms, please see:

http://processors.wiki.ti.com/index.php/Getting_started_with_IUNIVERSAL

http://processors.wiki.ti.com/index.php/OMAP-L137_iUniversal_%2B_ALSA_driver

If you plan on using the DSP drivers or want the DSPLib functions to run in the DSP, please see:

http://processors.wiki.ti.com/index.php/Example_application_using_DSP_Link_on_OMAPL1x

http://processors.wiki.ti.com/index.php/Example_DSPLIB/DSPLink_Application_on_OMAP-L1x

http://processors.wiki.ti.com/index.php/Audio_Soc_example

0 Lazy Donkey over 15 years ago in reply to Mariana

Prodigy 170 points

Hi Mariana,

I need the communication between Arm OS (Windows CE) and DSP OS (DSP/BIOS). Is there a windows ce driver available on arm side of omap-l137?

Thanks.

0 Mariana over 15 years ago in reply to Lazy Donkey

TI__Mastermind 24340 points

Hi KC,

Please use the WinCE forum for this question:

http://e2e.ti.com/support/embedded/f/353.aspx

There is some information about dspLink in this post:

http://e2e.ti.com/support/embedded/f/353/p/54978/203175.aspx#203175

but you might get more information if you post this question in the Wince forum.

0 Lazy Donkey over 15 years ago in reply to Mariana

Prodigy 170 points

Hi Mariana,

Thank you very much for the response. I have another dumb question, Can I this:

"Set up an EDMA operation by Arm Cpu, and the EDMA will create an interrupt on Dsp side when the operation is done" On Omap-L137.

What I want to do is:

1. Arm CPU set up an EDMA operation to transfer a block of memory from Arm's local RAM to Dsp local RAM.

2. When the operation is done, the EDMA will create an interrupt on the DSP intead of on the Arm.

3, DSP starts to process the data in DSP local RAM, and will finish within one second.

The operations will be repeated every second.

Is this possible on OMAP L137?

Thanks.

-KC

0 tlee over 15 years ago in reply to Lazy Donkey

TI__Guru 62975 points

KC,

The EDMA can generate completion interrupts for various transfers, but they are combined into one interrupt signal. This interrupt signal can be routed to ARM and/or DSP. You could route the completion interrupt to the DSP-only so that it satisfies your scheme.

-Tommy

0 Mukul Bhatnagar over 15 years ago in reply to Lazy Donkey

TI__Guru* 83935 points

Hi KC

Slight modifications/clarifications to the reply provided by Tommy

KC said:
"Set up an EDMA operation by Arm Cpu, and the EDMA will create an interrupt on Dsp side when the operation is done" On Omap-L137.

This is do-able but certainly not a common way of using the ARM and DSP with EDMA. You might have trouble implementing this if you are going to use TI software, as in general the assumption is that channels and TCCs (that will setup the IPR register and cause the interrupt if enabled) are upfront divided between ARM and DSP and you are not intermingling the resources.

KC said:
Arm CPU set up an EDMA operation to transfer a block of memory from Arm's local RAM to Dsp local RAM.

If you really meant that 8KB ARM RAM (at location 0xFFFF0000 ) , this is not accessible by EDMA , it can only be accessed by ARM. This can be inferred looking at the datasheet Table 3-4 or System Guide, System Interconnect chapter. So you cannot use EDMA to transfer to/from ARM RAM.

KC said:
When the operation is done, the EDMA will create an interrupt on the DSP intead of on the Arm.

This can be done. The EDMA controller has 2 completion interrupt, one mapped to ARM and one mapped to DSP (Recommend looking at Section 2.9.1.1 in the EDMA user guide). Region 0 interrupt goes to ARM and Region 1 interrupt goes to DSP. So you could setup your TCC values (completion code) and DRAE registers such that on completion of the ARM based EDMA tranfer, the EDMA3 interrupt triggered is Region 1 interrupt going to DSP.

Alternatively it also plausible to make use of the SYSCFG_CHIPINTx interrupts that are ARM to DSP interrupts (so you would get an EDMA3 completion interrupt to ARM after completion of a transfer and then in the EDMA ISR , you could trigger a SYSCFG_CHIPINTx interrupt to DSP). This might be higher latency implementation though.

KC said:
DSP starts to process the data in DSP local RAM, and will finish within one second.

Final time/performance would depend on the implementation and buffer size etc, but 1 second seems to be adequate time to accomplish something like this.

Hope this helps.
Regards

Mukul

Processors

Processors forum

ARM DSP communication in OMAPL137