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[AM5728] Confirm the timing characteristics for MMC1

Guru 24520 points

Hi TI Experts,

Please let me confirm the following questions.

[Question.1]
Customer would like to use UHS-1 SDR104, 4bit data, half cycle mode. I checked the datasheet on page 320, but there is not defined about SDR1043 , SDR1047 and SDR1048. So would you please provide us this specifications?

[Question.2]

Would  you please teach me the specification of "Setup" and "Hold" time of MMC1?

If you have any questions, please let me know.
Best regards.
Kaka

  • Hi,

    Timing requirements are specified in Section 7.23.1.6 UHS-I SDR104, 4-bit data, half-cycle in AM572x Data Manual.

    For anything beyond that, the TRM states the following for the MMC controllers integrated in AM572x SoC:
    - Full compliance with MMC/eMMC command/response sets as defined in the JC64 MMC/eMMC standard specification, v4.5.
    - Full compliance with SD command/response sets as defined in the SD Physical Layer specification v3.01
    - Full compliance with SDIO command/response sets and interrupt/read-wait suspend-resume operations as defined in the SD part E1 specification v3.00
    - Full compliance with SD Host Controller Standard Specification sets as defined in the SD card specification Part A2 v3.00

    Have you checked those documents?

    Best Regards,
    Yordan
  • Hi
    I know that there is the timing requirements for UHS-I SDR104, 4-bit data, half-cycle, but there is not defined the specification of setup time and hold time. Also I have checked those documentations, but I could not find about timing.

    This is why I would like to know those specifications.
    Best regards.
    Kaka
  • Regarding the SDR1043 , SDR1047 and SDR1048 values, please note that device is still undergoing characterization and the datasheet is being regularly updated. These values have not been available at the time of publication.