Can anyone point me to TI documentation for the cache control register operations on the 66ak2e05 SoC? We have an XEVMK2EX evaluation board, revision 1.0.2.2. The ARM v7A Architecture manual notes:
VMSA CP15 c9 register summary, reserved for cache and TCM control and performance
monitors
ARMv7 reserves some CP15 c9 encodings for IMPLEMENTATION DEFINED memory system functions, in particular:
• cache control, including lockdown
• TCM control, including lockdown
• branch predictor control.
This is followed by a list of generic 'c9' encodings. Nothing more is mentioned in the manual and the data sheet for the 66ak2e05 has nothing in it. I ask this because the Wind River BSP for this chip has the following code:
/* Set L2 cache latency */
mrc p15, 1, r0, c9, c0, 2 /* L2CTLR (w in ns 0) */
orr r0, r0, #(1 << 6) /* TRL (2 c) <A1>V Tag ram latency : 2 cycles */
orr r0, r0, #(3 << 0) /* DRL (4 c) <A1>V Data Ram latency: 4 cycles */
mcr p15, 1, r0, c9, c0, 2
isb
dsb
I see no "cache latency" terms in any TI document I have, so I was hoping someone could point me to something that explains the 'c9' encodings for the SoC.
Also, I am having a very difficult time setting up and enabling the MMU on the 66ak2e05. Every time I set up the descriptor table, base register and control register the set up runs well, but as soon as I enable the MMU, the chip crashes. Very strange.
Any help with this would be greatly appreciated.
Best regards, Mitch
