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Are external 10k pullups neccesary on MMC1 data/command lines when connected to eMMC device?

Other Parts Discussed in Thread: AM3352, CSD

Hello,

We designed a new board with AM3352 having a eMMC chip on MMC1 (pin-mux mode 2).

But we did not design the pullups on the eMMC lines, thinking the internal PU will be Ok.

Now we got the boards and have troubles, the bus is not running in 8 or 4 data width mode, only the mode 1 bit is working.

We rechecked the pin-muxing, measured the data-lines connection and layout, and everythink seems to be ok.

We aslo tried to reduce the clock, but behavior is the same. U-boot SW  seems also to work properly. The SD Card on MMC0 works with 4 data bits, but here we have the pullups...

So can be the mssing external pullups on the reason? 

Thanks

Jean-Luc

  • Hi,

    Have you double-checked that the internal pullups are enabled? Also I don't understand your statement about U-boot - does eMMC work properly there or not?
  • Hi Biser,
    Thanks for your answer
    Yes, all the pullups are enabled.
    eMMC does not work properly, eather in u-boot or in linux. Only the SD-Card attached to the MMC0 works properly.
    Best Regards
    Jean-Luc
  • This is strange. How long are the traces connecting to the eMMC? Do you have a serial resistor (~22Ohms) on the MMC_CLK line close to the processor?
  • Hi,

    here are my schematics around this eMMC.

    Yes we have this 22 Ohm. The traces are between 18-20 mm (Millimeters).

    We see that some NC balls have been used by the layouter to contact the right balls, but this is allowed according eMMC datasheets.

    Best Regards

  • Hello Jean-Luc,


    What is the eMMC version?  i.e. what is the value for VDDQ/VCCQ on the eMMC datasheet?

    Regards,

    a2g

  • I can see nothing wrong in the schematics. You are using a valid I/O set on the AM335X. What I cannot see are the I/O power supplies. VDDSHV1 and VDDSHV2 must be 3.3V.
  • Can you try to place a 10kOhm pullup on the CMD line?
  • We have two possible chips, one from Hynix and one from MICRON,

    Both are at least 4.5 compatible, both have VCC = 3.3V and dual  VCCq  (1.8 or 3.3V). And with both we have the same behavior.

    Regards

    Jean-Luc

  • We have all VDDSHVx = 3.3V.
    Ok, I will try to add a pullup on CMD line.
    But it works properly in mode 1 data bit (D0). We can see the manufacturer data, can correctly read/write in the whole domain. So for me the cmd and clk lines should be ok. Or not?
    Thanks
  • I checked the Micron datasheet and it recommends a stronger pullup on CMD. I don't dare ask you to pullup all 8 data lines, as this will likely be impossible over the trace lengths that you have. Also I seem to remember that CMD is open-drain in some situations. Pullup on CLK is definitely not needed.
  • By the way, is this a single board or you see the same issue on multiple boards?
  • what about pinmux settings in your U-Boot files?
    What version of U-boot are you using? from TI or from official from denx?
    FYI, bus width is 4-bit in U-Boot by default.
    Does U-boot recognize eMMC? ('mmc info')

    Regards,
    a2g
  • We have the same issue with our 15 prototypes, 5 having Micron and 10 having Hynix.

    Yes, U-boot recognizes the eMMC, mmc info command gives the correct data. The only issue is the bus width limited to 1.
    Our eMMC is also working under Linux if we force the data width to 1.

    We are using U-boot based on the Beagleboard, but adapted to our board (pinmux, ...).
    We were able to measure some data transfer on D0, but also on D1, D2, D3 lines during the eMMC initilization. So for me the pinmux is Ok. We also tried to enable the PD instead of PU on the datalines, it was worst, nothing anymore working, that's means PU are needed but may be our are not strong enough...

    Tomorrow I will try to add the external PU on cmd line, and will be back to you. Today I am not in the office, so cannot do it...

    Thanks again and Best Regards
    Jean-Luc
  • Hi all,

    I'm working together with Jean-Luc on this project. To be more specific we're using the TI flavour of U-Boot 2015.07. The config is indeed based on the config for TI AM335x boards with our own specific modifications.

    We now that U-Boot only works with 4-bit width by default (such as with the Beagleboard config). But also 4 is not working. We're always falling back to 1-bit width because the initialization code fails to compare the EXT_CSD when configured with more that 1-bit width.

    If it helps to identify the issue, here are the values we got when the driver compares the register values (2nd column is the correct value and 3rd one is the wrong value we get with 4-bit width set).

    Register 1-bit width value 4-bit width value
    EXT_CSD_PARTITIONING_SUPPORT 0x7 0x45
    EXT_CSD_HC_WP_GRP_SIZE 0x10 0x54
    EXT_CSD_REV 0x7 0x45
    EXT_CSD_HC_ERASE_GRP_SIZE 0x1 0x45
    EXT_CSD_SEC_CNT 0x0 0x44
    EXT_CSD_SEC_CNT+1 0x80 0xC4
    EXT_CSD_SEC_CNT+2 0x74 0x54
    EXT_CSD_SEC_CNT+3 0x0 0x44

    What is weird is that ALL our boards have the same behavior, even with two different MMC chip. On SKhynix one register is different  (EXT_CSD_REV=6) but the "mirrored" corresponding value is also different (i.e. 0x44 which is also the value minus 1...). That is, in U-Boot we ALWAYS have the same wrong values when trying more than one 1-bit width. But I can't come up with a good pattern out of those numbers.

    PS: with Linux, it fails also while trying to initialize to 8- and 4- bit bus width with error -84 (EILSEQ) because the bit DEB_EN is set (i.e. DATA End Bit Error from AM335x TRM). Maybe this is also a hint for missing pull-ups or other wrong lines?? (but seems to be OK after layout verifications)

    PS2: trying at lower speed doesn't seem to help. We went down to 600 kHz and still got the exact same behavior here.

    Thanks a lot for any suggestion here

  • Hi,

    Thanks for the details; did you tried with pull-up on cmd line? is it possible?

    FYI, we're using AM3352 with a similar eMMC (MTFC4GACA) but on MMC2 port. I'm using U-Boot 2016-01 (no differences for this interface). we have pull-up on data lines, clk and CMD (CMD line is working in 2 modes, one is open-drain mode...). I have no linux OS, I checked with u-boot only (info/read/write access) and this working well.

    If I'm not wrong, CSD register and other registers uses CLK/CMD lines only (I suppose this is not wrong because on our last prototype with a wrong eMMC with different Vccq, it was possible to get info but no read/write was possible)

    I can try removing pull-up on different lines on my board (prototype) just for testing purpose if you're interested in, but not today as it's too dangerous to do it on a Friday!!! Please let me know!

    Regards,
    a2g.

  • Hi a2g and Biser,

    Thanks for your reply.

    I just tried with 10k PU on cmd line -> no changes
    Then 10k PU on D1 and D2 -> no changes
    But I cannot easely contact D3...

    @a2g: Thanks for your proposal to remove your pull-up, it will be really great If you can and want do it to help us. ;-)

    Best regards and nice weekend
    Jean-Luc
  • Hi all,

    Thanks for your proposal of trying but no need to do it, we solved our issue now :-)

    In the end it was indeed a small pin mux issue. If you look at the table in my previous answer in binary mode, it shows that DAT1 was always 0 and DAT2 always 1.

           D3 2 1 0  D3 2 1 0

    0x07    0 0 0 0 : 0 1 1 1   (1 Bit Mode)
    0x45    0 1 0 0 : 0 1 0 1   (4 Bit Mode)

           D3 2 1 0  D3 2 1 0

    0x74    0 1 1 1 : 0 1 0 0
    0x54    0 1 0 1 : 0 1 0 0

           D3 2 1 0  D3 2 1 0
    0x80    1 0 0 0 : 0 0 0 0
    0xC4    1 1 0 0 : 0 1 0 0

    Someone gave the hint that this was exactly the default values from other pins (gpmc_ad1 and gpmc_ad2) that we plan to use as GPIO in the future. I checked again and saw that these pins (gpmc_ad0 to 3) were by default configured in Mode 1 (MMC1_DATx) by the processor. Changing those to Mode 7 solved then the issue!

    I wouldn't have thought that some of those pins had priority to our config, but this is probably because the ROM boot code configured these prior to our U-Boot code. But then why DAT0 and DAT4 were correctly taken into account is a mystery. Is it specified somewhere which MUX config has the priority over another? Because otherwise some other bugs can still hide with this kind of config (default with higher precedance).

    Now for the funny part we will anyway need to modify those pins for our next HW loop because we overlooked the fact that to boot from MMC1 exactly those pins need to be used (from 26.1.7.5.8 in TRM), so it would have solved our issue anyway ;-)

    Thanks again for your help!

  • Hello,
    I checked this morning by removing pull-ups on my board on CMD, CLK and DAT0-3 lines and everything is still working correctly (info, read/write blocks).
    So I can confirm that you would have had still an issue in your configuration as you found it! ^^
    Regards.
  • Hi a2g,

    Thanks a lot for your time and your confirmation. It was nice helping us solving this issue ;-)

    Have a nice day and best Regards.