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PLL settings in Linux kernel

Matt Burtch
Prodigy 160 points


Hello,

I'm trying to configure linux for a custom board we've developed and I'm having an issue finding where the clock rates for each PLL and it's sysclks are defined in the linux kernel.  I see the clock structure defined (for example in dm365.c) and the access functions to change the rate(in clock.c).  But I can't find where in the code the desired final rates are defined or, if it's done directly, the CLKDIVx values is set.   Is this not done by the kernel and the settings are left over from u-boot?

I'm sure it's a simple thing, I appreciate any help.

Thanks,

Matt

  • 0
    TI__Genius 9490 points

    Matt,

    I believe this is done on the UBL, but not certain.  I will move your post to the Linux forum as the right audience will see it there.

    regards,

    miguel

     

  • 0 in reply to Miguel A. Alanis
    Prodigy 160 points

    Thanks for the response and moving the post.

    I've looked at the uboot code and see where some of the dividers are set but it doesn't seem that they're all configured.  For example I only see PLL2DIV1 and 2 being set in the low level  initialization, but it seems like some others have been configured when I check /proc/davinci_clocks.  In case it's relevant I'm working with the DM365.

    It's possible I'm just looking past another place in u-boot where they're configured though.

    Thanks,

    -Matt

  • 0 in reply to Matt Burtch
    TI__Mastermind 19985 points

    Hi,

    The PLLs and the multiplier/dividers are configured in UBL. The device.c file is the one where the exact PLL settings are done. Following this, the uBoot generally reads the dividers to get the exact clock values.

    The kernel code also changes some dividers mainly based on the specific modules (for example, voice codec clock or video encoder clock).

    What exactly are you looking for? Do you want to change the clocks? If yes, then i would suggest to modify UBL code instead of kernel code.

    Regards,

    Anshuman

    PS: Please mark this post as verified if you think this has answered your question. Thanks.

  • 0 in reply to Anshuman Saxena
    Prodigy 160 points

    Thanks Anshuman, 

    That's what I was looking for. I've made the changes and the clocks all look good.  

  • 0 in reply to Matt Burtch
    Expert 1365 points

    Hi,

    I want to know the DDR clock frequency configured in dm368 UBL/kernel. I have also gone thru SPRUFG5A.pdf, PLLC1SYSCLK7/ PLLC2SYSCLK3 clock is use by DDR but none of users using these clock. I am attaching my dm368 cat proc/davinci_clocks output.

    Is there any other way to find DDR clock frequency?

    Please help me.

    3250.davinci_clocks.txt

     

  • 0 in reply to Ashwani
    Prodigy 240 points

    Just have a question , as i already in a similar situation which is actually I dont have UBL in my boot process, I skip it and use UBoot signed by AISGen tool

    the HW boots successfully and the UBoot copying the Linux kernal sucessfully but the kernal cannot start execute after that , so

    I guess that may be changes in the PLL settings needed to be included in the kernal Image.... what do you think ?

     

    Please note that in the old HW we have , we use a crystal 24 MHz and the boot sequence like : UBL + UBoot + Linux Kernal , and everything working properly

    now, in our new HW we use crystal 27 MHz , and the boot sequence should be as  : UBoot (signed by AISGen tool) + Linux kernal

    that is why i need to change the PLL settings in the linux kernal

  • 0 in reply to Matt Burtch
    Prodigy 10 points

    Hi Matt,

    I have the same problem. How/where did you change the PLL settings? dm365.c has just the data structure nothing more.