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C6678 Watch Dog Timer handle out of scope

murad qahwash
Genius 3770 points
Other Parts Discussed in Thread: SYSBIOS

Hello all,

C6678 EVM

bios_6_35_04_50

pdk_C6678_1_1_2_6

xdctools_3_25_03_72

I tested the watchdog timer in the timer example (C:\ti\pdk_C6678_1_1_2_6\packages\ti\csl\example\timer\timer_test.c) and added the following to reset the timer count value so the WDT never triggers an interrupt and that worked fine:

static Int32 test_wd_timer (Uint8 IntcInstance)

{

...

while(1)

{

WDT_reset();

}

...

}

where

void WDT_reset(void)

{

Uint16 loadVal;

/* Watchdog timer service key1 */

loadVal = CSL_TMR_WDTCR_WDKEY_CMD1;

CSL_tmrHwControl(wdTmr, CSL_TMR_CMD_LOAD_WDKEY, (Uint16 *)&loadVal);

/* Watchdog timer service key2 */

loadVal = CSL_TMR_WDTCR_WDKEY_CMD2;

CSL_tmrHwControl(wdTmr, CSL_TMR_CMD_LOAD_WDKEY, (Uint16 *)&loadVal);

}

When I added the same code to my sys/bios project, the WDT kept firing and the call to WDT_reset didn't work...when I break inside the WDT_reset, I noticed that the wdTmr handle is not valid anymore!...wdTmr is defined as a global handle same way in the timer_test.c code...

 

Regards,

Murad

  • 0
    TI__Mastermind 28085 points
    Hi,

    Have you include the CSL library on your SYS/BIOS(.cfg file) project? Please share your test project, i will try to resolve your issue.

    Thanks,
  • 0 in reply to Ganapathi Dhandapani95
    Genius 3770 points

    Dear Ganapathi,

    Thank you for your response.

    Yes, I am including the CSL Lib in my .cfg

    My project is using 5 cores and IPC and I can't include the full project. I am including the .cfg for core 0 which I am implementing the WDT at. Also, I had to partition the DDR3 among all core (we are to use all 8 cores later on)

    I need help verifying that I am using the correct memory map at some point (may be here or I can start a new post)

    core 0 memory map is:

            name            origin    length      used     unused   attr    fill

    ----------------------  --------  ---------  --------  --------  ----  --------

     L2SRAM                00800000   00080000  00075f12  0000a0ee  RW X

     MSMCSRAM_MASTER       0c000000   00100000  000d90e0  00026f20  RW X

     MSMCSRAM_SLAVE        0c100000   00100000  00000000  00100000  RW X

     MSMCSRAM_IPC          0c200000   00200000  00200000  00000000  RW X

     DDR3CORE0             80000000   12000000  01e33b99  101cc467  RW X

    Attached, please find the .cfg and the wdt.h and wdt.c

    Fullscreen wdt.c Download 
    /*----------------------------------------------------------------------------------*/
/* Copyrighted 2016 by Locus Location Systems								  		*/
/*                                                                            		*/
/* Filename: 	wtd.c  	                                                 	  		*/
/* version: 	1.00                                                          		*/
/* Description: Prepare config registers to perform HARD reset when WATCHDOG expires*/
/* Notes: 50 sec timeout															*/
/*----------------------------------------------------------------------------------*/
/* Revision History                                                           		*/
/* Ver      Date     History	   				                              		*/
/* ----  ----------  -------------------------------------------------------------- */
/* 1.00   01/24/2016  Original Version										  		*/
/* Author: Murad Qahwash									  				  		*/
#include "wdt.h"
#include <ti/sysbios/knl/Clock.h>

CSL_TmrHandle   wdTmr;

void WDT_init(void)
{
	CSL_PllcHandle  hPllc;
	CSL_TmrContext  context;
    CSL_TmrObj                  TmrObj;
    CSL_Status                  status;
    CSL_TmrHwSetup              hwSetup = CSL_TMR_HWSETUP_DEFAULTS;
    CSL_TmrEnamode              TimeCountMode = CSL_TMR_ENAMODE_CONT;
    Uint16  loadVal;

    Uint32 coreId;

    coreId = 0;//platform_get_coreid();

    //Unlock the kicker to ensure Boot configuration MMR is writeable
	CSL_BootCfgUnlockKicker();

    // Unlock registers for Core 0
//    CSL_BootCfgSetResetMuxLockStatus (coreId, 0);

	//Set the output mode for core x to ensure that the WD Timer generates a device reset to C6678
    CSL_BootCfgSetResetMuxOutputMode (coreId, 5);

	//Sets up the Key and Software Reset bit in Reset control register (RSTCTRL) contents. unlock RSTCFG register
//	hPllc = CSL_PLLC_open (0);    // Opens PLLC Instance 0
//	CSL_PLLC_setResetCtrlReg (hPllc, CSL_PLLC_RSTCTRL_VALID_KEY, 1);

	//Sets up the contents of Reset configuration register (RSTCFG) - Generate HARD reset when watchdog expires
//	CSL_PLLC_setResetCfgReg (hPllc, 0, 0, 0);

    // Lock registers for Core 0
//    CSL_BootCfgSetResetMuxLockStatus (coreId, 1);

	// Lock the kicker mechanism
    CSL_BootCfgLockKicker();


    // Prepare timer to act as a Watchdog timer
    //Clear local data structures
    memset(&TmrObj, 0, sizeof(CSL_TmrObj));

    /* Initialize the timer CSL module */
    CSL_tmrInit(NULL);

	/* Open the timer. */
    wdTmr = CSL_tmrOpen(&TmrObj, CSL_TMR_0, NULL, &status);
//    if (wdTmr == NULL)
//        return -1;

    /* Set the timer mode to WATCHDOG mode */
    hwSetup.tmrTimerMode    = CSL_TMR_TIMMODE_WDT;
    hwSetup.tmrPulseWidthLo = CSL_TMR_PWID_THREECLKS;
    hwSetup.tmrClksrcLo     = CSL_TMR_CLKSRC_INTERNAL; //(internal clock source = CPU/6 clock frequency = 1GHz/6)
    hwSetup.tmrClockPulseLo = CSL_TMR_CP_PULSE;
    hwSetup.tmrClockPulseHi = CSL_TMR_CP_PULSE;
    hwSetup.tmrIpGateLo     = CSL_TMR_CLOCK_INP_NOGATE;

    /* load the PRDLO */
    hwSetup.tmrTimerPeriodLo = 0x0;

    /* load the PRDHI */
    hwSetup.tmrTimerPeriodHi = 0x2;

    /* Configure the timer. */
    CSL_tmrHwSetup(wdTmr, &hwSetup);

    /* Reset the Timer */
//    CSL_tmrHwControl(wdTmr, CSL_TMR_CMD_RESET64, NULL);

    /* Start the timer in CONTINUOUS Mode. */
    CSL_tmrHwControl(wdTmr, CSL_TMR_CMD_START_WDT, (void *)&TimeCountMode);

    /* Watchdog timer service key1 */
    loadVal = CSL_TMR_WDTCR_WDKEY_CMD1;
    CSL_tmrHwControl(wdTmr, CSL_TMR_CMD_LOAD_WDKEY, (Uint16 *)&loadVal);

    /* Watchdog timer service key2 */
    loadVal = CSL_TMR_WDTCR_WDKEY_CMD2;
    CSL_tmrHwControl(wdTmr, CSL_TMR_CMD_LOAD_WDKEY, (Uint16 *)&loadVal);
}

void WDT_reset(void)
{
	Uint16  loadVal;

    /* Watchdog timer service key1 */
    loadVal = CSL_TMR_WDTCR_WDKEY_CMD1;
    CSL_tmrHwControl(wdTmr, CSL_TMR_CMD_LOAD_WDKEY, (Uint16 *)&loadVal);

    /* Watchdog timer service key2 */
    loadVal = CSL_TMR_WDTCR_WDKEY_CMD2;
    CSL_tmrHwControl(wdTmr, CSL_TMR_CMD_LOAD_WDKEY, (Uint16 *)&loadVal);
}
    wdt.h8168.DIAGNOSTX_MASTER.cfg

  • 0 in reply to murad qahwash
    Genius 3770 points

    Fullscreen 6403.wdt.c Download 
    /*----------------------------------------------------------------------------------*/
/* Copyrighted 2016 by Locus Location Systems								  		*/
/*                                                                            		*/
/* Filename: 	wtd.c  	                                                 	  		*/
/* version: 	1.00                                                          		*/
/* Description: Prepare config registers to perform HARD reset when WATCHDOG expires*/
/* Notes: 50 sec timeout															*/
/*----------------------------------------------------------------------------------*/
/* Revision History                                                           		*/
/* Ver      Date     History	   				                              		*/
/* ----  ----------  -------------------------------------------------------------- */
/* 1.00   01/24/2016  Original Version										  		*/
/* Author: Murad Qahwash									  				  		*/
#include "wdt.h"
#include <ti/sysbios/knl/Clock.h>

CSL_TmrHandle   wdTmr;

void WDT_init(void)
{
	CSL_PllcHandle  hPllc;
	CSL_TmrContext  context;
    CSL_TmrObj                  TmrObj;
    CSL_Status                  status;
    CSL_TmrHwSetup              hwSetup = CSL_TMR_HWSETUP_DEFAULTS;
    CSL_TmrEnamode              TimeCountMode = CSL_TMR_ENAMODE_CONT;
    Uint16  loadVal;

    Uint32 coreId;

    coreId = 0;//platform_get_coreid();

    //Unlock the kicker to ensure Boot configuration MMR is writeable
	CSL_BootCfgUnlockKicker();

    // Unlock registers for Core 0
//    CSL_BootCfgSetResetMuxLockStatus (coreId, 0);

	//Set the output mode for core x to ensure that the WD Timer generates a device reset to C6678
    CSL_BootCfgSetResetMuxOutputMode (coreId, 5);

	//Sets up the Key and Software Reset bit in Reset control register (RSTCTRL) contents. unlock RSTCFG register
//	hPllc = CSL_PLLC_open (0);    // Opens PLLC Instance 0
//	CSL_PLLC_setResetCtrlReg (hPllc, CSL_PLLC_RSTCTRL_VALID_KEY, 1);

	//Sets up the contents of Reset configuration register (RSTCFG) - Generate HARD reset when watchdog expires
//	CSL_PLLC_setResetCfgReg (hPllc, 0, 0, 0);

    // Lock registers for Core 0
//    CSL_BootCfgSetResetMuxLockStatus (coreId, 1);

	// Lock the kicker mechanism
    CSL_BootCfgLockKicker();


    // Prepare timer to act as a Watchdog timer
    //Clear local data structures
    memset(&TmrObj, 0, sizeof(CSL_TmrObj));

    /* Initialize the timer CSL module */
    CSL_tmrInit(NULL);

	/* Open the timer. */
    wdTmr = CSL_tmrOpen(&TmrObj, CSL_TMR_0, NULL, &status);
//    if (wdTmr == NULL)
//        return -1;

    /* Set the timer mode to WATCHDOG mode */
    hwSetup.tmrTimerMode    = CSL_TMR_TIMMODE_WDT;
    hwSetup.tmrPulseWidthLo = CSL_TMR_PWID_THREECLKS;
    hwSetup.tmrClksrcLo     = CSL_TMR_CLKSRC_INTERNAL; //(internal clock source = CPU/6 clock frequency = 1GHz/6)
    hwSetup.tmrClockPulseLo = CSL_TMR_CP_PULSE;
    hwSetup.tmrClockPulseHi = CSL_TMR_CP_PULSE;
    hwSetup.tmrIpGateLo     = CSL_TMR_CLOCK_INP_NOGATE;

    /* load the PRDLO */
    hwSetup.tmrTimerPeriodLo = 0x0;

    /* load the PRDHI */
    hwSetup.tmrTimerPeriodHi = 0x2;

    /* Configure the timer. */
    CSL_tmrHwSetup(wdTmr, &hwSetup);

    /* Reset the Timer */
//    CSL_tmrHwControl(wdTmr, CSL_TMR_CMD_RESET64, NULL);

    /* Start the timer in CONTINUOUS Mode. */
    CSL_tmrHwControl(wdTmr, CSL_TMR_CMD_START_WDT, (void *)&TimeCountMode);

    /* Watchdog timer service key1 */
    loadVal = CSL_TMR_WDTCR_WDKEY_CMD1;
    CSL_tmrHwControl(wdTmr, CSL_TMR_CMD_LOAD_WDKEY, (Uint16 *)&loadVal);

    /* Watchdog timer service key2 */
    loadVal = CSL_TMR_WDTCR_WDKEY_CMD2;
    CSL_tmrHwControl(wdTmr, CSL_TMR_CMD_LOAD_WDKEY, (Uint16 *)&loadVal);
}

void WDT_reset(void)
{
	Uint16  loadVal;

    /* Watchdog timer service key1 */
    loadVal = CSL_TMR_WDTCR_WDKEY_CMD1;
    CSL_tmrHwControl(wdTmr, CSL_TMR_CMD_LOAD_WDKEY, (Uint16 *)&loadVal);

    /* Watchdog timer service key2 */
    loadVal = CSL_TMR_WDTCR_WDKEY_CMD2;
    CSL_tmrHwControl(wdTmr, CSL_TMR_CMD_LOAD_WDKEY, (Uint16 *)&loadVal);
}

  • 0 in reply to murad qahwash
    Genius 3770 points
    Hello Ganapathi,

    Did you have a chance to look at my issue!

    Regards,

    Murad
  • 0 in reply to murad qahwash
    TI__Mastermind 28085 points
    Hi,

    Please provide your CCS project .zip file? I have tested the TI provide timer example and validate the watchdog timer, it is works properly.

    Thanks,
  • 0 in reply to Ganapathi Dhandapani95
    Genius 3770 points
    Hello Ganapathi,
    As I said above, the timer example WORKED!...when I added the same code to our sys/bios project (can't share), the WDT keeps timing out and WDT_reset() doesn't work...the timer handle inside WDT_reset() is not valid...I attached the .cfg, WDT.c, WDT.h above...do you see any error in my code?

    Regards,

    Murad
  • 0 in reply to murad qahwash
    Genius 3770 points

    HUA_WDT.zipHello Ganapathi,

    I added the WDT code to the Demo project that comes with MCSDK (C:\ti\mcsdk_2_01_02_06\demos\hua\evmc6678l) and I see the same problem...the WDT timeout is set to 25 second...you will see that the system will reset despite the call to  WDT_reset().

    Please let me know if you find the source to the problem mentioned above

    Regards,

    Murad

  • 0 in reply to murad qahwash
    Genius 3770 points
    Any idea/help!?
  • 0 in reply to murad qahwash
    TI__Guru** 116100 points

    Dear Murad,

    I've tried C6678 timer code for SYSBIOS based project and run successfully.

    C6678_timer_sysbios.zip

  • 0 in reply to Titusrathinaraj Stalin
    Genius 3770 points
    Thank you Titus for your email...I don't have a problem with the timer_test project...I meantioned that in previous posts above...my problem is resetting the WDT count as can be seen in the HUA_WDT.zip attached above...please use my attached project to see the problem (btw: I just added the WDT to the HUA demo project that comes with MCSDK)!


    Regards,

    Murad
  • 0 in reply to murad qahwash
    Genius 3770 points
    Hello all,
    Can I have some help fixing the problem in the project I attached (HUA_WDT.zip) above. This is really a show stopper for us and I appreciate and help!
  • 0 in reply to murad qahwash
    Genius 3770 points
    Thanks for Titus who resolved this issue as shown in:

    e2e.ti.com/.../1810906


    Regards,

    Murad
  • 0 in reply to murad qahwash
    TI__Guru** 116100 points

    Dear Murad,
    Thanks for giving the closed post here.