Hi
I am working on HS USB OTG Function Driver. The Function driver is working fine on omapl138evm and am1808 platforms. The device sometimes enumerate (Mass Storage & ECM class works) and most of times does not enumerate. In case of non enumeration, Device sends the maxP size as 0 instead of 64. Device is placing correct data in FIFO but unfortunately on wire we got wrong data. Only 2nd word (bDeviceClass, bDeviceSubClass, bDeviceProtocol, bMaxPacketSize0) data is wrong. Host puts three requests and finally device is suspended.
Jumper Settings: J23 = 1-2
I did following PAD and clock settings
#define M0_L (0)
#define IDIS_L (0 << 8)
#define IEN_L (1 << 8)
#define PD_L (1 << 3)
#define PU_L (3 << 3)
#define M0_H (0)
#define IDIS_H ((0 << 8)<<16)
#define IEN_H ((1 << 8)<<16)
#define PD_H ((1 << 3)<<16)
#define PU_H ((3 << 3)<<16)
#define CONTROL_PADCONF_UART3_TX_IRTX (0x480021A0)
#define CONTROL_PADCONF_HSUSB0_STP (0x480021A4)
#define CONTROL_PADCONF_HSUSB0_NXT (0x480021A8)
#define CONTROL_PADCONF_HSUSB0_DATA1 (0x480021AC)
#define CONTROL_PADCONF_HSUSB0_DATA3 (0x480021B0)
#define CONTROL_PADCONF_HSUSB0_DATA5 (0x480021B4)
#define CONTROL_PADCONF_HSUSB0_DATA7 (0x480021B8)
/* Mask values to clear and set mux mode fields. */
#define CONTROL_PADCONF_MUXLOW_MASK (0xFFFF)
#define CONTROL_PADCONF_MUXUP_MASK (0xFFFF0000)
#define CONTROL_PADCONF_HSUSB0_CLK_VAL (IEN_H | PD_H | M0_H ) /* hsusb0_clk */
#define CONTROL_PADCONF_HSUSB0_STP_VAL (IDIS_L | PU_L | M0_L ) /* hsusb0_stp */
#define CONTROL_PADCONF_HSUSB0_DIR_VAL (IEN_H | PD_H | M0_H ) /* hsusb0_dir */
#define CONTROL_PADCONF_HSUSB0_NXT_VAL (IEN_L | PD_L | M0_L ) /* hsusb0_nxt */
#define CONTROL_PADCONF_HSUSB0_DATA0_VAL (IEN_H | PD_H | M0_H ) /* hsusb0_data0 */
#define CONTROL_PADCONF_HSUSB0_DATA1_VAL (IEN_L | PD_L | M0_L ) /* hsusb0_data1 */
#define CONTROL_PADCONF_HSUSB0_DATA2_VAL (IEN_H | PD_H | M0_H ) /* hsusb0_data2 */
#define CONTROL_PADCONF_HSUSB0_DATA3_VAL (IEN_L | PD_L | M0_L ) /* hsusb0_data3 */
#define CONTROL_PADCONF_HSUSB0_DATA4_VAL (IEN_H | PD_H | M0_H ) /* hsusb0_data4 */
#define CONTROL_PADCONF_HSUSB0_DATA5_VAL (IEN_L | PD_L | M0_L ) /* hsusb0_data5 */
#define CONTROL_PADCONF_HSUSB0_DATA6_VAL (IEN_H | PD_H | M0_H ) /* hsusb0_data6 */
#define CONTROL_PADCONF_HSUSB0_DATA7_VAL (IEN_L | PD_L | M0_L ) /* hsusb0_data7 */
#define CM_ICLKEN1_CORE (0X48000000 + 0x4A10)
#define CM_AUTOIDLE1_CORE (0X48000000 + 0x4A30)
UINT32 temp32;
/* PADCONF settings for hsusb0_clk signal */
temp32 = READ32(CONTROL_PADCONF_UART3_TX_IRTX);
temp32 &= ~(CONTROL_PADCONF_MUXUP_MASK);
temp32 |= (CONTROL_PADCONF_HSUSB0_CLK_VAL);
WRITE32(CONTROL_PADCONF_UART3_TX_IRTX, temp32);
/* PADCONF settings for hsusb0_stp signal */
temp32 = READ32(CONTROL_PADCONF_HSUSB0_STP);
temp32 &= ~(CONTROL_PADCONF_MUXLOW_MASK);
temp32 |= (CONTROL_PADCONF_HSUSB0_STP_VAL);
WRITE32(CONTROL_PADCONF_HSUSB0_STP, temp32);
/* PADCONF settings for hsusb0_dir signal */
temp32 = READ32(CONTROL_PADCONF_HSUSB0_STP);
temp32 &= ~(CONTROL_PADCONF_MUXUP_MASK);
temp32 |= (CONTROL_PADCONF_HSUSB0_DIR_VAL);
WRITE32(CONTROL_PADCONF_HSUSB0_STP, temp32);
/* PADCONF settings for hsusb0_nxt signal */
temp32 = READ32(CONTROL_PADCONF_HSUSB0_NXT);
temp32 &= ~(CONTROL_PADCONF_MUXLOW_MASK);
temp32 |= (CONTROL_PADCONF_HSUSB0_NXT_VAL);
WRITE32(CONTROL_PADCONF_HSUSB0_NXT, temp32);
/* PADCONF settings for hsusb0_data0 signal */
temp32 = READ32(CONTROL_PADCONF_HSUSB0_NXT);
temp32 &= ~(CONTROL_PADCONF_MUXUP_MASK);
temp32 |= (CONTROL_PADCONF_HSUSB0_DATA0_VAL);
WRITE32(CONTROL_PADCONF_HSUSB0_NXT, temp32);
/* PADCONF settings for hsusb0_data1 signal */
temp32 = READ32(CONTROL_PADCONF_HSUSB0_DATA1);
temp32 &= ~(CONTROL_PADCONF_MUXLOW_MASK);
temp32 |= (CONTROL_PADCONF_HSUSB0_DATA1_VAL);
WRITE32(CONTROL_PADCONF_HSUSB0_DATA1, temp32);
/* PADCONF settings for hsusb0_data2 signal */
temp32 = READ32(CONTROL_PADCONF_HSUSB0_DATA1);
temp32 &= ~(CONTROL_PADCONF_MUXUP_MASK);
temp32 |= (CONTROL_PADCONF_HSUSB0_DATA2_VAL);
WRITE32(CONTROL_PADCONF_HSUSB0_DATA1, temp32);
/* PADCONF settings for hsusb0_data3 signal */
temp32 = READ32(CONTROL_PADCONF_HSUSB0_DATA3);
temp32 &= ~(CONTROL_PADCONF_MUXLOW_MASK);
temp32 |= (CONTROL_PADCONF_HSUSB0_DATA3_VAL);
WRITE32(CONTROL_PADCONF_HSUSB0_DATA3, temp32);
/* PADCONF settings for hsusb0_data4 signal */
temp32 = READ32(CONTROL_PADCONF_HSUSB0_DATA3);
temp32 &= ~(CONTROL_PADCONF_MUXUP_MASK);
temp32 |= (CONTROL_PADCONF_HSUSB0_DATA4_VAL);
WRITE32(CONTROL_PADCONF_HSUSB0_DATA3, temp32);
/* PADCONF settings for hsusb0_data5 signal */
temp32 = READ32(CONTROL_PADCONF_HSUSB0_DATA5);
temp32 &= ~(CONTROL_PADCONF_MUXLOW_MASK);
temp32 |= (CONTROL_PADCONF_HSUSB0_DATA5_VAL);
WRITE32(CONTROL_PADCONF_HSUSB0_DATA5, temp32);
/* PADCONF settings for hsusb0_data6 signal */
temp32 = READ32(CONTROL_PADCONF_HSUSB0_DATA5);
temp32 &= ~(CONTROL_PADCONF_MUXUP_MASK);
temp32 |= (CONTROL_PADCONF_HSUSB0_DATA6_VAL);
WRITE32(CONTROL_PADCONF_HSUSB0_DATA5, temp32);
/* PADCONF settings for hsusb0_data7 signal */
temp32 = READ32(CONTROL_PADCONF_HSUSB0_DATA7);
temp32 &= ~(CONTROL_PADCONF_MUXLOW_MASK);
temp32 |= (CONTROL_PADCONF_HSUSB0_DATA7_VAL);
WRITE32(CONTROL_PADCONF_HSUSB0_DATA7, temp32);
/* Enable HS OTG USB Interface Clock Control */
WRITE32(CM_ICLKEN1_CORE, READ32(CM_ICLKEN1_CORE) | 0x10);
/* Enable HS OTG USB Auto Clock Control */
WRITE32(AM3X_CM_AUTOIDLE1_CORE, READ32(AM3X_CM_AUTOIDLE1_CORE) | 0x10);
/* When no activity on L3 interconnect, clock is cut off. OTG_SYSCONFIG Register */
WRITE32(0x480AB000 + 0x404, 1);
/* PHY interface is 12pin, 8-bit SDR ULPI. OTG_INTERFSEL Register */
WRITE32(0x480AB000 + 0x40c, 1);
