Problems with SGMII link between C6678 and 88e1111

Hi Yurii,

Thanks for sharing!

Recently I had designed a custom board using C6670 that is similar with the C6678.

I follow the EVM6670 schematics to use CORECLK as 122.88MHz.

And then feed this 122.88MHz as the input of PASS PLL by clearing the PACLKSEL.

Fortunately, I haven't followed the settings in Table 2-24 of C6678's manual that is quite same as the Table 

2-13 of C6670's manual.

I just follow the GEL of EVM6670, it shows me as below

And everythings goes well.

I do not know why the settings in Table2-24 of C6678's manual fails. I am also curious about this.

But if the CORECLK remains 122.88MHz, you could try the GEL settings above and it may be OK.

By the way, using the value 122.88MHz may be convenient to get the value 30.72MHz that is LTE reltaed(I just only know about this and don't ask me why further). So C6670's EVM shows us the CORECLK as 122.88MHz because C6670 is dedicated to base station application. But C6678's EVM uses 100MHz as the CORECLK because C6678 is for more general usage. This is what I think.

Regards,

Feng

Hi Feng!

Feng Jin said:

I do not know why the settings in Table2-24 of C6678's manual fails

Further investigation showed that problem was not actually with the clock ) Documentation is correct and we acquired link even at 122.88 Mhz. All my previous thoughts were false. But correct PASS PLL setting is essential for proper SGMII initialization.

Yesterday we have loaded our new FPGA image with 100 MHz CORECLK over JTAG without power intervention. And everything works OK - SGMII link on. But when we put FPGA image on the flash (as we always did) and toggle power - we have no SGMII link. I think that the problem is somehow connected to PHY reset. Seems that our PHY is going out of reset with errors and its SerDes blocks become not functioning. PHY outputs correct K28.5 pattern on SGMII TX, and does not detect any errors in MDIO registers. But there is no link on SGMII and software reset does not help.

So the problem actually is not in documentation or hardware. My apologies to TI. I will post the correct solution as soon as it will be clear to us.

Best Regards,

Yurii

Hi Yurii,

Yurii Monakov said:

 I think that the problem is somehow connected to PHY reset. Seems that our PHY is going out of reset with errors and its SerDes blocks become not functioning. 

I also think correct power on reset sequence is critical to 88E1111. Actually, on my board C6670 is connected to two 88E1111 that each SGMII port connects one PHY. Firstly, the FPGA codes related to the PHY's power and reset is like below

else if(delay_5ms_cnt==1000000)
	begin
		DSP_JTAGSEL		<= 1'b0;
		PHY_VCC2V5_EN		<= 1'b1;
		PHY_VCC1V2_EN		<= 1'b1;
		PHY1_RST		<= 1'b0;
		PHY2_RST		<= 1'b0;
	end
else
	begin
		delay_5ms_cnt		<= delay_5ms_cnt;
	end

It means that FPGA turns on two PHYs' power and releases the two PHYs' reset at the same time. In this situation, PHY2 works OK but PHY1 fails. Even PHY1 can not link with PC through Ethernet cable.

Then I changed FPGA codes like below

else if(delay_5ms_cnt==1000000)
	begin
		DSP_JTAGSEL		<= 1'b0;
		PHY_VCC2V5_EN		<= 1'b1;
		PHY_VCC1V2_EN		<= 1'b1;
		delay_5ms_cnt		<= delay_5ms_cnt+1;
	end
else if(delay_5ms_cnt>1000000 & delay_5ms_cnt<1100000)
	begin
		delay_5ms_cnt		<= delay_5ms_cnt+1;
	end
else if(delay_5ms_cnt==1100000)
	begin
		PHY1_RST		<= 1'b1;
		PHY2_RST		<= 1'b1;
		delay_5ms_cnt		<= delay_5ms_cnt+1;
	end
else
	begin
		delay_5ms_cnt		<= delay_5ms_cnt;
	end

The new codes mean that FPGA turns on the two PHYs' power and wait for a few minutes then release the two PHYs' reset. Now the two PHYs can all  work OK!!

From what I met, I mean power on reset sequences is critical to 88E1111(the 88E1111's manual should contain this but I don't want to check further).

Hope this would be helpful.

Regards,

Feng

Hi Feng,

Thank you for the suggestion. I've talked to our HDL designers and they say that PHY reset is deasserted definitely after power supply is turned on.

Further investigation showed that PHY reset somehow appeared in the domain of peripherals that has no clock. So it was out of sync with 25 MHz clock. And probably PHY is going out of reset before 25 MHz clock arrived at its inputs.

Regards,

Yurii

Hi Yurii,

What you said that PHY is going out of reset before the clock is OK because of the reset deasserted signal's bad timing sounds quite reasonable.

After checking the 88E1111's manual, it told us as below

So the delay with minimum 10ms between power up and reset deasserted is mandatory.

Regards,
Feng