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SPI NOR Flash Boot

Godfrey Da Costa
Prodigy 70 points

Setup:

EVM6670L Rev 3A 

MCSDK_2.1.2.5

Version: 5.2.1.00018 

My application uses only MCSM and L2 and doesn't use DDR. I have followed the procedure to generate the byte swapped .dat file for my application and flashed NOR successfully.  After flashing the board I set the switches on the EVM (SW3: OFF ON OFF OFF, SW4: ON ON ON ON, SW5: ON ON OFF ON, SW6: OFF ON ON ON).

I have tried SPI mode = 0 as well (i.e. SW6: ON ON ON ON).  

Once I power the board, the application doesn't run. If I connect the debugger I see that it has stopped at

20b0a270:   00034000            SPKERNEL      0x 0

What is certain is that the NOR flash is read as I can see the boot parameter table that is at address 0 in NOR. I can see the boot parameter table in the memory reserved for RBL in L2 (at 0x8F3680).

0x00000050 0x00000032
0x00024020 0x00180001 0x00000004 0x00000001 0x00000320
0x003201F4 0x00000400 0x00000000 0x00000000 0x00000000
0x00000000 0x00000000 0x00000000 0x00000000

To ensure that the table is not created by RBL, I scribbled some words in the image and I can see the scribbled words in the table in L2. But, I see that none of the sections in L2 are written from the boot table. I have checked the first section and it is clearly not written.

Is there any way I can get the symbol table for the RBL supplied for the chip for me to debug? Or could you suggest how I could proceed?

Many thanks

Gdc

 

  • 0
    Prodigy 70 points
    I've found the reason for the failure.

    b2i2c deletes two lines at the front which messes up the boot table.

    I'm now able to boot the application.
  • 0 in reply to Godfrey Da Costa
    TI__Guru* 81335 points

    Welcome to the TI E2E forum. I hope you will find many good answers here and in the TI.com documents and in the TI Wiki Pages (for processor issues). Be sure to search those for helpful information and to browse for the questions others may have asked on similar topics (e2e.ti.com). Please read all the links below my signature.

  • 0 in reply to Raja
    Prodigy 70 points
    Hi Raja,

    I have a related question but perhaps it should be be a new thread. Please let me know if it should be.

    I am trying to do a mult-core boot. Since I use only L2 nd MCSM I have a piece of code in my application on core 0 which copies the image to cores 1 to 3. The other cores don't boot even though the magic addresses are written correctly and an IPC interrupt is generated.

    In order to debug the boot procedure, I run in NO-BOOT mode. What I see when I attach the emulator is that cores 1-3 run IDLE as expected. I then stop cores 1-3 and check if the IPC interrupt is registered. I see IF4 is registered but yet core 1 for instance is still stuck running the IDLE instruction in the RBL. Is there anything else I ought to do?

    Thanks

    Godfrey
  • 0 in reply to Godfrey Da Costa
    TI__Guru* 81335 points

    Once your primary core has booted, all you need to do is populate the magic addresses for the secondary core and issue an IPC interrupt. This process of populating the magic address and then issue IPC interrupts to wake up ssecondarycores has been described in the srioboot_helloworld.c file in the SDK

    I have provided a snapshot of the code here for your reference:

    /* Unlock the chip registers */
DEVICE_REG32_W(KICK0, 0x83e70b13);
DEVICE_REG32_W(KICK1, 0x95a4f1e0);

/* Writing the entry address to other cores */
for (core = 1; core < pform_info.cpu.core_count; core++)
{
sprintf(boot_msg, "\r\n\r\nBooting Hello World image on Core %d from Core 0 ...", core);
write_uart(boot_msg);

DEVICE_REG32_W(BOOT_MAGIC_ADDR(core), (uint32_t)write_boot_magic_number);

/* Delay 1 sec */
platform_delay(1);
}
for (core = 1; core < pform_info.cpu.core_count; core++)
{
/* IPC interrupt other cores */
DEVICE_REG32_W(IPCGR(core), 1);
platform_delay(1000);
}
  • 0 in reply to Raja
    Prodigy 70 points
    Hi Raja,

    I had done exactly what you suggest. What I really wanted to know was whether it is possible to halt the core at the IDLE instruction so that I can debug the boot code. I couldn't go beyond the IDLE even if IPC interrupt for that core was generated by core 0. If the core is executing (running and not halted by the emulator), it does seem to take the interrupt and go past the IDLE instruction.

    I have been able to fix the multi-core boot issue. I now face another problem when the NOR start address in the Boot Parameter Table is 0x10000. offset of 0x400 works fine.

    In order to debug the issue it would have been very useful to have the symbol table. Would it be possible to get the symbol table? I am using a C6670 and the RBL version is v1.11 Wed Jan 26 07:22:03 2011 i2c mac srio pcie vusr spi.

    Let me know if you need any further information.

    Thanks

    Godfrey
  • 0 in reply to Godfrey Da Costa
    TI__Guru* 81335 points

    Hi Godfrey,

    Here is an working example of how to convert an .out file to boot table that you can boot on C6670/C6678 device and document of how to create the boot image.

    http://e2e.ti.com/cfs-file.ashx/__key/communityserver-discussions-components-files/639/0675.SPI_5F00_Bootloader.zip

    http://e2e.ti.com/cfs-file.ashx/__key/communityserver-discussions-components-files/639/8015.Booting_5F00_from_5F00_SPI-NOR_5F00_C6678.pdf

    Please give this a try and let us know if you had any issues. Thank you.