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[C5535] Leak current on SPI_TX pin

Guru 24520 points

Hi TI Experts,

Please let me confirm the following question.

[Question]
When customer used the pull down register for SPI_TX pin (K1), the current consumption was reduced approximately 1mA. So it seems that there is leak current on this pin.
- Is this phenomenon correct behavior as C5535?

- What is cause of this phenomenon? 

- Do you have any solution to reduce the power consumption with software workaround?

  ->This pin has not IPD and IPU.

If you need more information or have any questions, please let me know.
Best regards.
Kaka

  • Hi Kaka-san,

    Which function is being is used ? could you let me know your EBSR settings too.

    Yes pin K1 doesn’t have IPD and IPU. In general for I/O pins, it can be configured as output, but you cannot apply software configurations until bootloader completes and application code runs - During boot IO current could be higher than after configuring for low power. This pin at reset will be input and in LCD mode.

    Regards

     Vasanth

  • Hi Vasanth,

    Thank you for your response.
    I will confirm your questions to my customer. If I get answers from them, I will post.

    By the way, according to the datasheet on page 68, the LCD_D[1]/SPI_TX pin(K1) will be Hi-Z at reset.
    So does this mean that "This pin at reset will be input and in LCD mode"?

    Best regards.
    Kaka
  • Hi Vasanth,

    I got feedback from my customer.
    They have used the "0x1820" for EBSR settings. i.e. They have already set the SPI mode.

    Also the K1 pin on C5535eZdsp short to GND, the current consumption is reduced on DVDDIO. So it seems that there was the leak current on this pin even though it set the K1 as output direction.

    If you have any questions, please let me know.

    Best regards.

    Kaka

  • Hi Kaka-san, 

    I confirm this is the LCD_D[1]/SPI_TX pin(K1) will be Hi-Z at reset. 

    The default values after reset will be LCD and will be in input mode, but I will confirm back again on this. Sorry about the confusion. 

    Regards

     Vasanth

  • Hi Vasanth,

    Thank you for your response and your confirming.
    I am waiting your feedback.
    Also this behavior is not limited at reset time. In normal operation, we could confirm that the current consumption will reduce about 0.2mA.
    So, we would like to confirm whether there is the leak current on this pin even thoght it was set as output direction(SPI_TX).

    If you have any questions, please let me know.
    Best regards.
    Kaka
  • Hi Kaka-san, 

    Can you reconfirm on EBSR setting, LSB config doesn't seem right.  

    With respect to K1 pin, If its configured as SPI, then this pin will be an output pin & I do not think  pull down is required. I will further check on this and get back to you.  I might need more information from you.

      

      Regards

     Vasanth

  • Hi Vasanth,

    Thank you for your response.
    When I evaluated the C5535eZdsp, the PPMODE bits on EBSR was Mode1. i.e. I set this pin as SPI mode.
    I agree with your opinion but I could not understand why I confirmed this phenomenon.

    Best regards.
    Kaka
  • Hi Vasanth,

    Do you have any updates for this topic? I am waiting for your feedback.

    Best regards.
    kaka
  • Hi Kaka-san,

    There was little bit of confusion with respect to your last statement,  "I agree with your opinion but I could not understand why I confirmed this phenomenon"  I had thought you will get back.

    But anyway for the scenario that you had mentioned, have you recreated this in any of the TI platform ? this would help us. Please let me know.

    Regards

     Vasanth

  • Hi Vasanth,

    I apologize for your confusion. I was waiting your feedback.
    I agreed with your opinion that if set the pin as output, there is not any leak current.
    But I have checked whether there is any leak current on SPI_TX pin with using the C5535eZdsp, I could confirm that it was reduced the current consumption on DVDDIO by pull down the SPI_TX pin. So I could not understand why I confirmed this even though the SPI_TX pin was set as mode1(SPI mode).

    My customer thought that if C5535 does not send any data on pin, it will be Hi-z. This is why there is leak current on this pin. How do you think?

    Yes, as I mentioned on above, I could recreate this phenomenon. In my customer situation, the SPI_TX pin is floating. On the other hand, the SPI_TX pin on C5535eZdsp is connected to SPI Flash. There is some differences with situation. Customer confirmed the reducing the current consumption about 1mA by this, but I could confirmed that the DVDDIO line on C5535eZdsp reduced the current consumption approximately 0.2mA by that.

    Best regards.
    Kaka

  • Hi Kaka-san,

    We were able to re-create the scenario and with initial checks it looks like this pin when un-driven gets into High impedance mode.

    Also when we tried driving SPI_TX data and paused during transfer, that is when SPI_TX was driven to known '1' or '0' we observed the current did reduce ( this can be observed when character count in SPI status register 2 is non-zero value ).

    Also, may I know which peripherals are been used in this application ?

    Regards

     Vasanth

  • Hi Vasanth,

    Thank you for your kindly supports.
    I am not sure that the peripherals which my customer used. They might use the SPI(SPI NOR Flash and it used for boot), MMC(for SD cards), I2S(for Codec), and ADC(for button).

    I hope this answers your question.

    Best regards.
    Kaka
  • Hi Kaka-san,

     

    Based on our debug, the result is more inclined towards SPI_TX pin been driven to high impedance state, even when set to SPI mode (in EBSR register) but SPI_TX pin not driven to 1 or 0 from SPI controller.

     

    Below are two options that we are thinking about to solve this issue.

     

    1. Hardware :

      Pull down the SPI_TX pin through 10K resistor value.

    2. Software:

      Configure in EBSR to SPI mode-1 and initiate SPI transfer (transmit operation), during middle of transfer stop the SPI clock, this way the SPI_TX has driven to high/low and holds this value. At this stage if you read the SPI status 2 register the CCNT should be non-zero value. Although this is not straight forward approach, but still we observed leakage current reduction. I suggest you to try this in your current platform and confirm.

     

    Please let me know if you have any further questions on the above two options.

     

    Regards

    Vasanth

  • Hi Vasanth,
    Thank you for your response.
    I will inform this to my customer. Do you have a plan to add this to the datasheet or errata?

    If you have any questions, please let me know.
    Best regards.
    Kaka