Change of GPMC Interface between Boot code and Application code

Hi,

Are you intending to execute code directly from flash?

Hi Biser,

As of now we load the boot code in the NOR Flash and execute it from NOR Flash EXCEPT the NOR IMAGE FINDING portion of the BOOT CODE. That portion of the boot code is copied from NOR FLASH [CS0] to 0x40300000 and executed from there.

As far as application code is concerned for CS1 NOR FLASH, we have compiled the code and global constants to NOR Flash and INITIALIZED and UNITIALIZED GLOBAL and STATIC Variables in the on board DDR3.

Regards.

Biser,

Do i need to initialize for CS0 as well as it will already be initialize based on the SYSBOOT config.

Regards

Actually you are right. You cannot execute from CS0 and reinitialize it at the same time. You can check what initialization is done by ROM code in section 26.1.7.2 of the AM335X TRM Rev. M.

The most important thing is that in Non-Muxed NOR Boot only addresses up to A11 are pinmuxed to GPMC mode by ROM code. If you need to execute more than 4kBytes code from CS0 you will need to pinmux higher addresses from these first 4k. In this case you must also be aware that external logic is needed to isolate the upper address lines (A12–A27) of the NOR flash from the AM335X pins and drive them low during non-muxed NOR boot. Similarly for Muxed NOR Boot, address lines A16 and above to the memory are not controlled by the ROM and need to be managed externally during boot to ensure proper addressing to the all memory signals.

Thanks Biser for all the info...

Hi Biser,

One doubt still existing:-

In order to initialize CS1 line in the boot code, I need to disable the CS0 line in the boot code.

So can I take this portion of the code in the OCMC arm and execute it from there so that accessing CS0 line is no longer required.

I do not know whether you will entertain my .cmd file but still I am pasting it:-

    .ram_code: { bl_norexec.obj(.text)} load > NOR_MEM, run > 0x40300000
                 LOAD_START(ram_code_load_start)
                 RUN_START(ram_code_run_start)
                 SIZE(ram_code_size)

so if bl_norexec.obj is where this change CS line is there, I will execute it from OCMC Ram.

Will be thankful for this response for completion...

I don't see why you should disable CS0 to configure CS1. These are two separate regions. Typically for a given CSx you should configure the corresponding registers GPMC_CONFIG[1:7]_x, and when everything is configured, enable CSx by setting GPMC_CONFIG7_x[6] CSVALID=1