LISA configuration:
We are using the micron DDR3L(MT41K256M16HA-125), 512MB * 4 = 2GB
DDR1(EMIF-1) lines are connected to the two DDR chip of each 512MB, total-1GB(same as beagle x15).
DDR2(EMIF-2) lines are connected to other two DDR chip of each 512MB, total-1GB(same as beagle x15).
LISA configuration done as given below in board.c file(../board/ti/beagle_x15/board.c):
static const struct dmm_lisa_map_regs beagle_x15_lisa_regs = {
.dmm_lisa_map_0 = 0x80540100,
.dmm_lisa_map_1 = 0xA0540100,
.dmm_lisa_map_2 = 0xC0540200,
.dmm_lisa_map_3 = 0xE0540200,
.is_ma_present = 0x1
};
Mtest is failing in this configuration if give the address more than 9fffffff, mtest will pass till 9fffffff(512MB).
Can you please let us know what should be the LISA configuration if we are using the 4*512MB = 2GB.
EMIF1 and EMIF2 register configuration are:
.sdram_config_init = 0x61851b32,
.sdram_config = 0x61851b32,
.sdram_config2 = 0x00000000,
.ref_ctrl = 0x00001035,
.ref_ctrl_final = 0x00001035,
.sdram_tim1 = 0xCCCF369B,
.sdram_tim2 = 0x2E907FDA,
.sdram_tim3 = 0x501F88AF,
.read_idle_ctrl = 0x00050000,
.zq_config = 0x0007190B,
.temp_alert_config = 0x00000000,
.emif_ddr_phy_ctlr_1_init = 0x0024400B,
.emif_ddr_phy_ctlr_1 = 0x0E24400A,
.emif_ddr_ext_phy_ctrl_1 = 0x10040100,
.emif_ddr_ext_phy_ctrl_2 = 0x00BB00BB,
.emif_ddr_ext_phy_ctrl_3 = 0x00BB00BB,
.emif_ddr_ext_phy_ctrl_4 = 0x00BB00BB,
.emif_ddr_ext_phy_ctrl_5 = 0x00BB00BB,
.emif_rd_wr_lvl_rmp_win = 0x00000000,
.emif_rd_wr_lvl_rmp_ctl = 0x00000000,
.emif_rd_wr_lvl_ctl = 0x00000000,
.emif_rd_wr_exec_thresh = 0x00000305
Tim1, Tim2 and Tim3 configuration is done based on 1066(533MHz) with reference of micron DDR datasheet.
Thanks,
Shekar
